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author | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-22 16:11:52 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-15 17:57:18 +0000 |
commit | 4d56a0625516ba436903d59d9c0a4a13827d89be (patch) | |
tree | 764641e18971d6e4e54a9e0142595dc3104da106 /src/soc/intel | |
parent | 5bb15f1a4d18bafaf51b17fd9ea6d861f2b9ebd2 (diff) | |
download | coreboot-4d56a0625516ba436903d59d9c0a4a13827d89be.tar.xz |
nb/intel/broadwell: Add an option for where verstage starts
Previously broadwell used a romcc bootblock and starting verstage in
romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also
possible to have a separate verstage.
This selects using a separate verstage by default but still keeps the
option around to use verstage in romstage.
With a separate verstage the romstage becomes an RW stage.
The mrc.bin however is only added to the RO COREBOOT fmap region as it
requires to be run at a specific offset. This means that coreboot will
have to jump from a RW region to the RO region for that binary and
back to that RW region after that binary is done initializing the
memory.
Change-Id: I900233cadb3c76da329fb98f93917570e633365f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30384
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r-- | src/soc/intel/broadwell/Kconfig | 25 | ||||
-rw-r--r-- | src/soc/intel/broadwell/Makefile.inc | 2 | ||||
-rw-r--r-- | src/soc/intel/broadwell/romstage/raminit.c | 7 |
3 files changed, 32 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 9dd2f4f414..b685391af9 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -67,9 +67,25 @@ config PCIEXP_L1_SUB_STATE bool default y +config BROADWELL_VBOOT_IN_BOOTBLOCK + depends on VBOOT + bool "Start verstage in bootblock" + default y + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + help + Broadwell can either start verstage in a separate stage + right after the bootblock has run or it can start it + after romstage for compatibility reasons. + Broadwell however uses a mrc.bin to initialse memory which + needs to be located at a fixed offset. Therefore even with + a separate verstage starting after the bootblock that same + binary is used meaning a jump is made from RW to the RO region + and back to the RW region after the binary is done. + config VBOOT select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_STARTS_IN_ROMSTAGE + select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK config MMCONF_BASE_ADDRESS hex @@ -141,6 +157,13 @@ config MRC_BIN_ADDRESS hex default 0xfffa0000 +# The UEFI System Agent binary needs to be at a fixed offset in the flash +# and can therefore only reside in the COREBOOT fmap region +config RO_REGION_ONLY + string + depends on VBOOT + default "mrc.bin" + endif # HAVE_MRC config PRE_GRAPHICS_DELAY diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index eab8b37ba2..40017eb3ec 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -49,6 +49,7 @@ romstage-y += pei_data.c ramstage-y += pmutil.c romstage-y += pmutil.c smm-y += pmutil.c +verstage-y += pmutil.c ramstage-y += ramstage.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c ramstage-y += sata.c @@ -70,6 +71,7 @@ ramstage-y += tsc_freq.c romstage-y += tsc_freq.c smm-y += tsc_freq.c postcar-y += tsc_freq.c +verstage-y += tsc_freq.c bootblock-$(CONFIG_USBDEBUG) += usb_debug.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 8d43907f8a..fc8b7c6984 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -45,6 +45,8 @@ void raminit(struct pei_data *pei_data) struct memory_info *mem_info; pei_wrapper_entry_t entry; int ret; + struct cbfsf f; + uint32_t type = CBFS_TYPE_MRC; broadwell_fill_pei_data(pei_data); @@ -77,7 +79,10 @@ void raminit(struct pei_data *pei_data) } /* Determine if mrc.bin is in the cbfs. */ - entry = cbfs_boot_map_with_leak("mrc.bin", CBFS_TYPE_MRC, NULL); + if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0) + die("mrc.bin not found!"); + /* We don't care about leaking the mapping */ + entry = (pei_wrapper_entry_t)rdev_mmap_full(&f.data); if (entry == NULL) { printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); return; |