diff options
| author | Matt Delco <delco@chromium.org> | 2018-07-27 14:17:29 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-20 15:53:54 +0000 |
| commit | 9084c3c31bf62bc5c38cf5a1edbd830e407675c6 (patch) | |
| tree | 37c65dd3869bf2a727ffa77e8764b4953490b788 /src/soc/intel | |
| parent | 9557a34abeb8c2101a853f49e20a3671c4551aef (diff) | |
| download | coreboot-9084c3c31bf62bc5c38cf5a1edbd830e407675c6.tar.xz | |
soc/intel/skylake: add CPPC support
ACPI 5.0 defines a method _CPC for "Continuous Performance Control" (CPPC).
Linux has a driver that enables features like speed shift without
consulting ACPI. Other OSes instead rely on this information and need a
_CPC present. Prior to this change performance in Win10 never exceeds
80% and MSR 0x770 is 0, while with this change (and enabling eist) higher
speeds can be achieved and the MSR value is now 1.
Change-Id: Ib7e0ae13f4b664b51e42f963e53c71f8832be062
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/27673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/skylake/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/skylake/acpi.c | 13 |
2 files changed, 12 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 1060c2a11b..74f86d1439 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -2,6 +2,7 @@ ifeq ($(CONFIG_SOC_INTEL_SKYLAKE),y) subdirs-y += nhlt subdirs-y += romstage +subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 2c06b4bea1..284cd92053 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -29,6 +29,7 @@ #include <cpu/x86/smm.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> +#include <cpu/intel/common/common.h> #include <cpu/intel/turbo.h> #include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> @@ -520,6 +521,12 @@ void generate_cpu_entries(struct device *device) printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); + if (config->eist_enable && config->speed_shift_enable) { + struct cppc_config cppc_config; + cpu_init_cppc_config(&cppc_config, 2 /* version 2 */); + acpigen_write_CPPC_package(&cppc_config); + } + for (cpu_id = 0; cpu_id < numcpus; cpu_id++) { for (core_id = 0; core_id < cores_per_package; core_id++) { if (core_id > 0) { @@ -535,11 +542,13 @@ void generate_cpu_entries(struct device *device) generate_c_state_entries(is_s0ix_enable, max_c_state); - if (config->eist_enable) + if (config->eist_enable) { /* Generate P-state tables */ generate_p_state_entries(core_id, cores_per_package); - + if (config->speed_shift_enable) + acpigen_write_CPPC_method(); + } acpigen_pop_len(); } } |