summaryrefslogtreecommitdiff
path: root/src/soc/intel
diff options
context:
space:
mode:
authorPaul Menzel <pmenzel@molgen.mpg.de>2018-09-18 11:29:24 +0200
committerRonald G. Minnich <rminnich@gmail.com>2018-10-30 02:10:44 +0000
commitb06f8ddfe8c0e18f962f8b5507a40f4ef430ffc1 (patch)
tree7a40e00d1ce1f95368cf49aa2a121e12e08372df /src/soc/intel
parent1ed082bc8bfd557b80f620ff4bf7a98d39a3c7bc (diff)
downloadcoreboot-b06f8ddfe8c0e18f962f8b5507a40f4ef430ffc1.tar.xz
Documentation/riscv: Improve `index.md`
1. Add dot/period to the end of sentences 2. Remove blank line at the end of the file 3. Break lines after 75 characters 4. Use RISC-V spelling 5. Add comma for clarity Change-Id: Icbe803dfbe92ca7850204a1a9f7175befe9c8bcf Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/28654 Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions