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| author | Fehér Roland Ádám <feherneoh@gmail.com> | 2018-10-17 18:41:49 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 19:42:11 +0000 |
| commit | d5a8155f1b90531201ae578e019182823614bcea (patch) | |
| tree | a4e627043783e167e140621a171143a6a4fbe0fc /src/soc/intel | |
| parent | 967b84d5ea78886f0f076c19f998650fcb94288e (diff) | |
| download | coreboot-d5a8155f1b90531201ae578e019182823614bcea.tar.xz | |
util/inteltool: Fix LynxPoint (non-LP) GPIO register map
The GPIO register dumper code for the LynxPoint family PCH chips
(Intel 8 Series and C220 Series) was incorrectly using a
shortened version of the LynxPoint-LP GPIO register map.
Switched to the correct register map for the affected chipsets.
Change-Id: I394a198bbb6628915cb73cabc5c8ff808579a07f
Signed-off-by: Fehér Roland Ádám <feherneoh@gmail.com>
Reviewed-on: https://review.coreboot.org/29167
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
0 files changed, 0 insertions, 0 deletions