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| author | Stefan Tauner <stefan.tauner@gmx.at> | 2018-08-19 20:02:05 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-09-18 10:36:12 +0000 |
| commit | de028789fda806b358538613d33a9a0a020d3d8c (patch) | |
| tree | f40bb6803cbef05f1e8346e2629f8b0d0dd8ce2c /src/soc/intel | |
| parent | c703beb31d8f95c1e861cb4007b02c3eaaf93c33 (diff) | |
| download | coreboot-de028789fda806b358538613d33a9a0a020d3d8c.tar.xz | |
cpu/*/car: fix ancient URL explaining XIP range run-time calculation
Change-Id: I49526b6aafb516a668b7b5e983a0372e3d26a8fc
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/broadwell/romstage/cache_as_ram.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc index fd9f829286..6d3d6dd7f6 100644 --- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc +++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc @@ -134,7 +134,7 @@ clear_mtrrs: xorl %edx, %edx /* * IMPORTANT: The following calculation _must_ be done at runtime. See - * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html */ movl $_program, %eax andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax |