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| author | Aamir Bohra <aamir.bohra@intel.com> | 2018-07-01 00:13:29 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-12-10 12:07:43 +0000 |
| commit | df47e1c3e590c4aeb2e1dcd32dca194f91327e3f (patch) | |
| tree | eee5a8b17496782aa8e70ea11ca8cb67711b842e /src/soc/intel | |
| parent | 2b35780a277bd48bb2133a59ac920b3e03658c4e (diff) | |
| download | coreboot-df47e1c3e590c4aeb2e1dcd32dca194f91327e3f.tar.xz | |
mb/intel/icelake_rvp: Fill Icelake U and Y RVP devicetree parameters
This implementation configures below parameters:
1. Enable SaGv, isclk.
2. Set Pcie rootport enable, Clock source usage and clkreq.
3. Configure SATA and LPSS controllers parameters.
4. Enable CNVI controller, configure Wifi end device under PCIE RP1.
5. Add TPM device support under GSPI1.
Change-Id: I585e82799eea0bad19ad2c94d6b4b3024f930ed4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/icelake/chip.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index c8653b2f8e..3e2b78acd6 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -115,6 +115,7 @@ struct soc_intel_icelake_config { uint16_t usb3_wake_enable_bitmap; /* SATA related */ + uint8_t SataEnable; uint8_t SataMode; uint8_t SataSalpSupport; uint8_t SataPortsEnable[8]; |