src: Add missing include <stdint.h>

Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29312
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

8 files changed, 16 insertions, 3 deletions

diff --git a/src/soc/intel/apollolake/include/soc/heci.h b/src/soc/intel/apollolake/include/soc/heci.h
index 1151321445..ac28b14cee 100644
--- a/src/soc/intel/apollolake/include/soc/heci.h
+++ b/src/soc/intel/apollolake/include/soc/heci.h
@@ -17,6 +17,8 @@
 #ifndef _SOC_APOLLOLAKE_HECI_H_
 #define _SOC_APOLLOLAKE_HECI_H_
 
+#include <stdint.h>
+
 enum sec_status {
 	SEC_STATE_RESET = 0,
 	SEC_STATE_INIT,
diff --git a/src/soc/intel/baytrail/include/soc/iomap.h b/src/soc/intel/baytrail/include/soc/iomap.h
index bb6b4bbdea..11c01e311d 100644
--- a/src/soc/intel/baytrail/include/soc/iomap.h
+++ b/src/soc/intel/baytrail/include/soc/iomap.h
@@ -16,7 +16,6 @@
 #ifndef _BAYTRAIL_IOMAP_H_
 #define _BAYTRAIL_IOMAP_H_
 
-
 /*
  * Memory Mapped IO bases.
  */
@@ -79,6 +78,8 @@
 #define SMBUS_BASE_ADDRESS		0xefa0
 
 #ifndef __ACPI__
+#include <stdint.h>
+
 /* Read Top of Low Memory (BMBOUND) */
 uint32_t nc_read_top_of_low_memory(void);
 #endif
diff --git a/src/soc/intel/braswell/include/soc/iomap.h b/src/soc/intel/braswell/include/soc/iomap.h
index a07490280e..c61983b446 100644
--- a/src/soc/intel/braswell/include/soc/iomap.h
+++ b/src/soc/intel/braswell/include/soc/iomap.h
@@ -17,7 +17,6 @@
 #ifndef _SOC_IOMAP_H_
 #define _SOC_IOMAP_H_
 
-
 /*
  * Memory Mapped IO bases.
  */
@@ -81,6 +80,8 @@
 #define SMBUS_BASE_ADDRESS		0xefa0
 
 #ifndef __ACPI__
+#include <stdint.h>
+
 /* Read Top of Low Memory (BMBOUND) */
 uint32_t nc_read_top_of_low_memory(void);
 #endif
diff --git a/src/soc/intel/cannonlake/include/soc/lpc.h b/src/soc/intel/cannonlake/include/soc/lpc.h
index a4e42bddf3..ea72675dbc 100644
--- a/src/soc/intel/cannonlake/include/soc/lpc.h
+++ b/src/soc/intel/cannonlake/include/soc/lpc.h
@@ -17,6 +17,8 @@
 #ifndef _SOC_CANNONLAKE_LPC_H_
 #define _SOC_CANNONLAKE_LPC_H_
 
+#include <stdint.h>
+
 /* PCI Configuration Space (D31:F0): LPC */
 #define SCI_IRQ_SEL		(7 << 0)
 #define SCIS_IRQ9		0
diff --git a/src/soc/intel/common/block/include/intelblocks/smm.h b/src/soc/intel/common/block/include/intelblocks/smm.h
index f560f24e2b..c04ec46800 100644
--- a/src/soc/intel/common/block/include/intelblocks/smm.h
+++ b/src/soc/intel/common/block/include/intelblocks/smm.h
@@ -17,6 +17,8 @@
 #ifndef SOC_INTEL_COMMON_BLOCK_SMM_H
 #define SOC_INTEL_COMMON_BLOCK_SMM_H
 
+#include <stdint.h>
+
 /*
  * This common code block relies on each specific SOC defining the macro
  * ENABLE_SMI_PARAMS for the values needed for SMI enabling on the
diff --git a/src/soc/intel/common/block/include/intelblocks/vmx.h b/src/soc/intel/common/block/include/intelblocks/vmx.h
index 7f65b599b4..b93ceeb8c1 100644
--- a/src/soc/intel/common/block/include/intelblocks/vmx.h
+++ b/src/soc/intel/common/block/include/intelblocks/vmx.h
@@ -14,6 +14,8 @@
 #ifndef SOC_INTEL_COMMON_BLOCK_VMX_H
 #define SOC_INTEL_COMMON_BLOCK_VMX_H
 
+#include <stdint.h>
+
 struct vmx_param {
 	uint8_t enable;
 };
diff --git a/src/soc/intel/fsp_baytrail/include/soc/iomap.h b/src/soc/intel/fsp_baytrail/include/soc/iomap.h
index bb6b4bbdea..11c01e311d 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/iomap.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/iomap.h
@@ -16,7 +16,6 @@
 #ifndef _BAYTRAIL_IOMAP_H_
 #define _BAYTRAIL_IOMAP_H_
 
-
 /*
  * Memory Mapped IO bases.
  */
@@ -79,6 +78,8 @@
 #define SMBUS_BASE_ADDRESS		0xefa0
 
 #ifndef __ACPI__
+#include <stdint.h>
+
 /* Read Top of Low Memory (BMBOUND) */
 uint32_t nc_read_top_of_low_memory(void);
 #endif
diff --git a/src/soc/intel/icelake/include/soc/lpc.h b/src/soc/intel/icelake/include/soc/lpc.h
index df781be54d..dfcfa353c8 100644
--- a/src/soc/intel/icelake/include/soc/lpc.h
+++ b/src/soc/intel/icelake/include/soc/lpc.h
@@ -16,6 +16,8 @@
 #ifndef _SOC_ICELAKE_LPC_H_
 #define _SOC_ICELAKE_LPC_H_
 
+#include <stdint.h>
+
 /* PCI Configuration Space (D31:F0): LPC */
 #define SCI_IRQ_SEL		(7 << 0)
 #define SCIS_IRQ9		0