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| author | Furquan Shaikh <furquan@chromium.org> | 2017-05-06 13:01:32 -0700 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2017-05-08 19:14:23 +0200 |
| commit | e411f8eb72e3674d82f03fceaca27af4e64a9aaf (patch) | |
| tree | 17fe33df2f1019885e671a55057b6dbdae1c0a69 /src/soc/intel | |
| parent | 1ea7cce8ae8fbc8a14a3ddfdee3f81a5e0e50031 (diff) | |
| download | coreboot-e411f8eb72e3674d82f03fceaca27af4e64a9aaf.tar.xz | |
soc/intel/skylake: Enable MTRR check
Change a4b11e5c90 (soc/intel/skylake: Perform CPU MP Init
before FSP-S Init) dropped mtrr_check while re-organizing
code. Add the check back after MTRR setup is performed.
BUG=b:36656098
TEST=Verified that MTRR check is done after setup on poppy.
Change-Id: I440405c58c470ffa338be386d84870635530a031
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/skylake/cpu.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 0b1b9af6ce..2f356355b0 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -523,6 +523,7 @@ static void soc_post_cpus_init(void *unused) { if (mp_run_on_all_cpus(&x86_setup_mtrrs_with_detect, 1000) < 0) printk(BIOS_ERR, "MTRR programming failure\n"); + x86_mtrr_check(); } int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) |