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authorXiang Wang <wxjstz@126.com>2018-07-12 14:56:05 +0800
committerMartin Roth <martinroth@google.com>2018-07-17 18:09:43 +0000
commit5fed693a52ed9746900ce58ec12a2b245f08202e (patch)
tree29bc3c68250a8365e0c25134f4383b07d29bb93f /src/soc/lowrisc
parent745e58a5ee50373276924349524a2594599e8bb5 (diff)
downloadcoreboot-5fed693a52ed9746900ce58ec12a2b245f08202e.tar.xz
riscv: add support for modifying compiler options
Each HART of a SoC like fu540 supports a different ISA. In order for the coreboot's code can run on each core, need to modify the compile options. So add this code. Change-Id: Ie33edc175e612846d4a74f3cbf7520d4145cb68b Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Philipp Hug <philipp@hug.cx>
Diffstat (limited to 'src/soc/lowrisc')
-rw-r--r--src/soc/lowrisc/lowrisc/Kconfig12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/lowrisc/lowrisc/Kconfig b/src/soc/lowrisc/lowrisc/Kconfig
index 528e7444f7..71078b5c25 100644
--- a/src/soc/lowrisc/lowrisc/Kconfig
+++ b/src/soc/lowrisc/lowrisc/Kconfig
@@ -11,4 +11,16 @@ config SOC_LOWRISC_LOWRISC
if SOC_LOWRISC_LOWRISC
+config RISCV_ARCH
+ string
+ default "rv64imafd"
+
+config RISCV_ABI
+ string
+ default "lp64d"
+
+config RISCV_CODEMODEL
+ string
+ default "medany"
+
endif