diff options
| author | Daisuke Nojiri <dnojiri@chromium.org> | 2014-12-03 12:09:58 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-28 10:20:42 +0200 |
| commit | 599c32d8ef908f0b9723eb864f0a8695f6a76758 (patch) | |
| tree | 9ca90891f2907cf89235bd21ed87f48f90467331 /src/soc/marvell/bg4cd/include | |
| parent | efc6aa0eb928a27e625eb62ca848de7e191c5b67 (diff) | |
| download | coreboot-599c32d8ef908f0b9723eb864f0a8695f6a76758.tar.xz | |
marvell/bg4cd: merge verstage into bootblock
If verified boot is enabled, merge verstage into bootblock. This also
requires custom bootblock code to actually call into verstage.
[pg: modified to match upstream]
BUG=chrome-os-partner:32631
BRANCH=ToT
TEST=booted on cosmos development board.
Change-Id: I53251aac966ee15da24232c23fefa636de8b253b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2b8ada263017b46afa755b5acb759574184dba06
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: Ia0e1236357aa32bf553fb8cc98f3a8d29de17f45
Original-Reviewed-on: https://chromium-review.googlesource.com/229795
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10008
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/marvell/bg4cd/include')
| -rw-r--r-- | src/soc/marvell/bg4cd/include/soc/memlayout.ld | 30 |
1 files changed, 18 insertions, 12 deletions
diff --git a/src/soc/marvell/bg4cd/include/soc/memlayout.ld b/src/soc/marvell/bg4cd/include/soc/memlayout.ld index 45cf3950c3..d6244b3f03 100644 --- a/src/soc/marvell/bg4cd/include/soc/memlayout.ld +++ b/src/soc/marvell/bg4cd/include/soc/memlayout.ld @@ -24,16 +24,22 @@ SECTIONS { - DRAM_START(0x00000000) - RAMSTAGE(0x00200000, 128K) - POSTRAM_CBFS_CACHE(0x01000000, 1M) - - SRAM_START(0x80000000) - TTB(0x80000000, 16K) - BOOTBLOCK(0x80004004, 16K - 4) - VBOOT2_WORK(0x80008000, 16K) - OVERLAP_VERSTAGE_ROMSTAGE(0x8000C000, 40K) - PRERAM_CBFS_CACHE(0x80016000, 4K) - STACK(0x80017000, 4K) - SRAM_END(0x80018000) + SRAM_START(0x20000) + + BOOTBLOCK(0x20000, 40K) + /* there is no VERSTAGE because it's built into bootblock */ + + PRERAM_CBFS_CACHE(0x2A000, 8K) + STACK(0x2C000, 8K) + VBOOT2_WORK(0x2E000, 16K) + + SRAM_END(0x40000) + + DRAM_START(0x40000) + + RAMSTAGE(0x40000, 128K) + POSTRAM_CBFS_CACHE(0x60000, 1M) + + ROMSTAGE(0xF7A40000, 32K) + TTB(0xF7A48000, 16K) } |