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authorJulius Werner <jwerner@chromium.org>2017-06-21 15:38:51 -0700
committerJulius Werner <jwerner@chromium.org>2018-02-02 22:19:14 +0000
commit6d643cf722872dfe25a3fb6f8b149642b93a1adc (patch)
tree35dd38bf895e3b36dc358b6ee1cb64f13371355d /src/soc/marvell
parent8e08a844f7528ec6778e1e063f5cc2d53fbbf2e9 (diff)
downloadcoreboot-6d643cf722872dfe25a3fb6f8b149642b93a1adc.tar.xz
rockchip: Correct UART reference clock value
The Rockchip UARTs are tied directly to the 24MHz oscillator and are thus clocked with exactly 24MHz. The reasons why our code instead uses some 23.xxMHz value have long been lost in time. For the current shared 8250 implementation, the baud rate divisor for 115200 would be the same. Correcting this does make the information in the coreboot table more accurate and help payloads chose a better divisor, though. Change-Id: Ieceb07760178f8ddbb5936f8742b78f8def4072d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/23556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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