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author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2018-05-25 15:49:33 -0700 |
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committer | Martin Roth <martinroth@google.com> | 2018-06-13 14:24:31 +0000 |
commit | 572f4988ddb3b85bdce019de7d6a594bea070bfb (patch) | |
tree | cdd97252e963587a34a7fa4833102daa0354119e /src/soc/mediatek/common/cbmem.c | |
parent | 9b05af367fde33fc620c4cd759c2b09cdc036cc9 (diff) | |
download | coreboot-572f4988ddb3b85bdce019de7d6a594bea070bfb.tar.xz |
soc/amd/stoneyridge/southbridge.c: Fix saving _SWS parameters
PM1 and GPE0 are being stored directly to NVS, when actually what should
be saved is the index of the bit responsible for waking. Fix the procedures
and add definitions to the actual IO addresses to be read when recording
status and enable registers.
BUG=b:75996437
TEST=Build and boot grunt. Once in OS, execute a sleep and a wake. See the
message indicating which indexes are being save in NVS for _SWS. Try sleep
stress test, verify that the index is different from that of power button.
Change-Id: I8bafc7bb7dd66e7f0eb8499e748535bbdcac5f53
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/mediatek/common/cbmem.c')
0 files changed, 0 insertions, 0 deletions