soc/mediatek/mt8183: add dphy reset after setting lanes number

Add dphy reset after setting lanes number to avoid dphy fifo error.

BUG=b:139150763
BRANCH=kukui
TEST=Boots correctly on kukui

Change-Id: Ib83576f3700ef98c90f0b4dd101dcaa237d562f9
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

1 files changed, 8 insertions, 0 deletions

diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c
index 2b4fac7d42..d60abdb964 100644
--- a/src/soc/mediatek/common/dsi.c
+++ b/src/soc/mediatek/common/dsi.c
@@ -392,6 +392,12 @@ static void mtk_dsi_send_init_commands(const u8 *buf)
 	}
 }
 
+static void mtk_dsi_reset_dphy(void)
+{
+	setbits_le32(&dsi0->dsi_con_ctrl, DPHY_RESET);
+	clrbits_le32(&dsi0->dsi_con_ctrl, DPHY_RESET);
+}
+
 int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
 		 const u8 *init_commands)
 {
@@ -407,6 +413,8 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
 	struct mtk_phy_timing phy_timing;
 	mtk_dsi_phy_timing(data_rate, &phy_timing);
 	mtk_dsi_rxtx_control(mode_flags, lanes);
+	mdelay(1);
+	mtk_dsi_reset_dphy();
 	mtk_dsi_clk_hs_mode_disable();
 	mtk_dsi_config_vdo_timing(mode_flags, format, lanes, edid, &phy_timing);
 	mtk_dsi_clk_hs_mode_enable();