Change all clrsetbits_leXX() to clrsetbitsXX()

This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.

This patch was created by running

 sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'

across the codebase and cleaning up formatting a bit.

Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

1 files changed, 6 insertions, 6 deletions

diff --git a/src/soc/mediatek/common/mtcmos.c b/src/soc/mediatek/common/mtcmos.c
index fa0b23a353..fbc2d7dfe7 100644
--- a/src/soc/mediatek/common/mtcmos.c
+++ b/src/soc/mediatek/common/mtcmos.c
@@ -46,17 +46,17 @@ static void mtcmos_power_on(const struct power_domain_data *pd)
 	write32(&mtk_spm->poweron_config_set,
 		(SPM_PROJECT_CODE << 16) | (1U << 0));
 
-	setbits_le32(pd->pwr_con, PWR_ON);
-	setbits_le32(pd->pwr_con, PWR_ON_2ND);
+	setbits32(pd->pwr_con, PWR_ON);
+	setbits32(pd->pwr_con, PWR_ON_2ND);
 
 	while (!(read32(&mtk_spm->pwr_status) & pd->pwr_sta_mask) ||
 	       !(read32(&mtk_spm->pwr_status_2nd) & pd->pwr_sta_mask))
 		continue;
 
-	clrbits_le32(pd->pwr_con, PWR_CLK_DIS);
-	clrbits_le32(pd->pwr_con, PWR_ISO);
-	setbits_le32(pd->pwr_con, PWR_RST_B);
-	clrbits_le32(pd->pwr_con, pd->sram_pdn_mask);
+	clrbits32(pd->pwr_con, PWR_CLK_DIS);
+	clrbits32(pd->pwr_con, PWR_ISO);
+	setbits32(pd->pwr_con, PWR_RST_B);
+	clrbits32(pd->pwr_con, pd->sram_pdn_mask);
 
 	while (read32(pd->pwr_con) & pd->sram_ack_mask)
 		continue;