mediatek/mt8183: Fix RTC initialization flow

1. Fix RTC lpd settings. Rewrite powerkeys after lpd init
   to enable low power detect function.
2. Rearrange RTC initialization flow.
3. Add return status for rtc_init.
4. Add log if calling pwrap_write or pwrap_read fail.
5. Increase timeout time to resolve unexpected timeout.

BUG=b:127405695
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: I6f26edd6699c2f6d9af80c285b70742b44407136
Signed-off-by: Ran Bi <ran.bi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>

2 files changed, 91 insertions, 51 deletions

diff --git a/src/soc/mediatek/common/include/soc/rtc_common.h b/src/soc/mediatek/common/include/soc/rtc_common.h
index 41e772e9ed..e3c231bfc4 100644
--- a/src/soc/mediatek/common/include/soc/rtc_common.h
+++ b/src/soc/mediatek/common/include/soc/rtc_common.h
@@ -22,6 +22,11 @@
 #include <delay.h>
 #include <rtc.h>
 #include <timer.h>
+#include <soc/pmic_wrap_common.h>
+
+#define RTCTAG			"[RTC]"
+#define rtc_info(fmt, arg ...)	printk(BIOS_INFO, RTCTAG "%s,%d: " fmt, \
+				__func__, __LINE__, ## arg)
 
 /*
  * Default values for RTC initialization
@@ -93,13 +98,46 @@ enum {
 	RTC_STATE_INIT		= 2
 };
 
+/* RTC error code */
+enum {
+	RTC_STATUS_OK	= 0,
+	RTC_STATUS_POWERKEY_INIT_FAIL,
+	RTC_STATUS_WRITEIF_UNLOCK_FAIL,
+	RTC_STATUS_OSC_SETTING_FAIL,
+	RTC_STATUS_GPIO_INIT_FAIL,
+	RTC_STATUS_HW_INIT_FAIL,
+	RTC_STATUS_REG_INIT_FAIL,
+	RTC_STATUS_LPD_INIT_FAIL
+};
+
 /* external API */
 int rtc_busy_wait(void);
 int rtc_write_trigger(void);
 int rtc_writeif_unlock(void);
-void rtc_xosc_write(u16 val);
+int rtc_xosc_write(u16 val);
 int rtc_reg_init(void);
-u8 rtc_check_state(void);
 void rtc_boot_common(void);
 
+static inline s32 rtc_read(u16 addr, u16 *rdata)
+{
+	s32 ret;
+
+	ret = pwrap_read(addr, rdata);
+	if (ret < 0)
+		rtc_info("pwrap_read fail: ret=%d\n", ret);
+
+	return ret;
+}
+
+static inline s32 rtc_write(u16 addr, u16 wdata)
+{
+	s32 ret;
+
+	ret = pwrap_write(addr, wdata);
+	if (ret < 0)
+		rtc_info("pwrap_write fail: ret=%d\n", ret);
+
+	return ret;
+}
+
 #endif /* SOC_MEDIATEK_RTC_COMMON_H */
diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c
index fd40cb5d1a..3b1a600c15 100644
--- a/src/soc/mediatek/common/rtc.c
+++ b/src/soc/mediatek/common/rtc.c
@@ -26,10 +26,10 @@ int rtc_busy_wait(void)
 	stopwatch_init_usecs_expire(&sw, RTC_CBUSY_TIMEOUT_US);
 
 	do {
-		pwrap_read(RTC_BBPU, &bbpu);
+		rtc_read(RTC_BBPU, &bbpu);
 		/* Time > 1sec, time out and set recovery mode enable.*/
 		if (stopwatch_expired(&sw)) {
-			printk(BIOS_INFO, "[RTC] BBPU CBUSY time out !!\n");
+			rtc_info("BBPU CBUSY time out !!\n");
 			return 0;
 		}
 	} while (bbpu & RTC_BBPU_CBUSY);
@@ -39,17 +39,17 @@ int rtc_busy_wait(void)
 
 int rtc_write_trigger(void)
 {
-	pwrap_write(RTC_WRTGR, 1);
+	rtc_write(RTC_WRTGR, 1);
 	return rtc_busy_wait();
 }
 
 /* unlock rtc write interface */
 int rtc_writeif_unlock(void)
 {
-	pwrap_write(RTC_PROT, RTC_PROT_UNLOCK1);
+	rtc_write(RTC_PROT, RTC_PROT_UNLOCK1);
 	if (!rtc_write_trigger())
 		return 0;
-	pwrap_write(RTC_PROT, RTC_PROT_UNLOCK2);
+	rtc_write(RTC_PROT, RTC_PROT_UNLOCK2);
 	if (!rtc_write_trigger())
 		return 0;
 
@@ -67,39 +67,40 @@ int rtc_get(struct rtc_time *time)
 {
 	u16 value;
 
-	pwrap_read(RTC_TC_SEC, &value);
+	rtc_read(RTC_TC_SEC, &value);
 	time->sec = value;
-	pwrap_read(RTC_TC_MIN, &value);
+	rtc_read(RTC_TC_MIN, &value);
 	time->min = value;
-	pwrap_read(RTC_TC_HOU, &value);
+	rtc_read(RTC_TC_HOU, &value);
 	time->hour = value;
-	pwrap_read(RTC_TC_DOM, &value);
+	rtc_read(RTC_TC_DOM, &value);
 	time->mday = value;
-	pwrap_read(RTC_TC_MTH, &value);
+	rtc_read(RTC_TC_MTH, &value);
 	time->mon = value;
-	pwrap_read(RTC_TC_YEA, &value);
+	rtc_read(RTC_TC_YEA, &value);
 	time->year = (value + RTC_MIN_YEAR_OFFSET) % 100;
 
 	return 0;
 }
 
 /* set rtc xosc setting */
-void rtc_xosc_write(u16 val)
+int rtc_xosc_write(u16 val)
 {
 	u16 bbpu;
 
-	pwrap_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1);
+	rtc_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1);
 	udelay(200);
-	pwrap_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2);
+	rtc_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2);
 	udelay(200);
 
-	pwrap_write(RTC_OSC32CON, val);
+	rtc_write(RTC_OSC32CON, val);
 	udelay(200);
 
-	pwrap_read(RTC_BBPU, &bbpu);
+	rtc_read(RTC_BBPU, &bbpu);
 	bbpu |= RTC_BBPU_KEY | RTC_BBPU_RELOAD;
-	pwrap_write(RTC_BBPU, bbpu);
-	rtc_write_trigger();
+	rtc_write(RTC_BBPU, bbpu);
+
+	return rtc_write_trigger();
 }
 
 /* initialize rtc related registers */
@@ -107,45 +108,47 @@ int rtc_reg_init(void)
 {
 	u16 irqsta;
 
-	pwrap_write(RTC_IRQ_EN, 0);
-	pwrap_write(RTC_CII_EN, 0);
-	pwrap_write(RTC_AL_MASK, 0);
-	pwrap_write(RTC_AL_YEA, 1970 - RTC_MIN_YEAR);
-	pwrap_write(RTC_AL_MTH, 1);
-	pwrap_write(RTC_AL_DOM, 1);
-	pwrap_write(RTC_AL_DOW, 4);
-	pwrap_write(RTC_AL_HOU, 0);
-	pwrap_write(RTC_AL_MIN, 0);
-	pwrap_write(RTC_AL_SEC, 0);
-
-	pwrap_write(RTC_DIFF, 0);
-	pwrap_write(RTC_CALI, 0);
+	rtc_write(RTC_IRQ_EN, 0);
+	rtc_write(RTC_CII_EN, 0);
+	rtc_write(RTC_AL_MASK, 0);
+	rtc_write(RTC_AL_YEA, 1970 - RTC_MIN_YEAR);
+	rtc_write(RTC_AL_MTH, 1);
+	rtc_write(RTC_AL_DOM, 1);
+	rtc_write(RTC_AL_DOW, 4);
+	rtc_write(RTC_AL_HOU, 0);
+	rtc_write(RTC_AL_MIN, 0);
+	rtc_write(RTC_AL_SEC, 0);
+
+	rtc_write(RTC_DIFF, 0);
+	rtc_write(RTC_CALI, 0);
 	if (!rtc_write_trigger())
 		return 0;
 
-	pwrap_read(RTC_IRQ_STA, &irqsta);  /* read clear */
+	rtc_read(RTC_IRQ_STA, &irqsta);  /* read clear */
 
 	/* init time counters after resetting RTC_DIFF and RTC_CALI */
-	pwrap_write(RTC_TC_YEA, RTC_DEFAULT_YEA - RTC_MIN_YEAR);
-	pwrap_write(RTC_TC_MTH, RTC_DEFAULT_MTH);
-	pwrap_write(RTC_TC_DOM, RTC_DEFAULT_DOM);
-	pwrap_write(RTC_TC_DOW, RTC_DEFAULT_DOW);
-	pwrap_write(RTC_TC_HOU, 0);
-	pwrap_write(RTC_TC_MIN, 0);
-	pwrap_write(RTC_TC_SEC, 0);
+	rtc_write(RTC_TC_YEA, RTC_DEFAULT_YEA - RTC_MIN_YEAR);
+	rtc_write(RTC_TC_MTH, RTC_DEFAULT_MTH);
+	rtc_write(RTC_TC_DOM, RTC_DEFAULT_DOM);
+	rtc_write(RTC_TC_DOW, RTC_DEFAULT_DOW);
+	rtc_write(RTC_TC_HOU, 0);
+	rtc_write(RTC_TC_MIN, 0);
+	rtc_write(RTC_TC_SEC, 0);
 
 	return rtc_write_trigger();
 }
 
-u8 rtc_check_state(void)
+static u8 rtc_check_state(void)
 {
 	u16 con;
 	u16 pwrky1;
 	u16 pwrky2;
 
-	pwrap_read(RTC_CON, &con);
-	pwrap_read(RTC_POWERKEY1, &pwrky1);
-	pwrap_read(RTC_POWERKEY2, &pwrky2);
+	rtc_read(RTC_CON, &con);
+	rtc_read(RTC_POWERKEY1, &pwrky1);
+	rtc_read(RTC_POWERKEY2, &pwrky2);
+
+	rtc_info("con=%x, pwrkey1=%x, pwrkey2=%x\n", con, pwrky1, pwrky2);
 
 	if (con & RTC_CON_LPSTA_RAW)
 		return RTC_STATE_INIT;
@@ -180,15 +183,14 @@ void rtc_boot_common(void)
 		break;
 	case RTC_STATE_INIT:
 	default:
-		if (!rtc_init(0))
+		if (rtc_init(0))
 			rtc_init(1);
 		break;
 	}
 
-	pwrap_read(RTC_IRQ_STA, &irqsta);  /* Read clear */
-	pwrap_read(RTC_BBPU, &bbpu);
-	pwrap_read(RTC_CON, &con);
+	rtc_read(RTC_IRQ_STA, &irqsta);  /* Read clear */
+	rtc_read(RTC_BBPU, &bbpu);
+	rtc_read(RTC_CON, &con);
 
-	printk(BIOS_INFO, "[RTC] irqsta = %x", irqsta);
-	printk(BIOS_INFO, " bbpu = %#x, con = %#x\n", bbpu, con);
+	rtc_info("irqsta=%x, bbpu=%x, con=%x\n", irqsta, bbpu, con);
 }