diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-12-02 22:03:27 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-04 14:11:17 +0000 |
| commit | 55009af42c39f413c49503670ce9bc2858974962 (patch) | |
| tree | 099e9728bfe8066999de4d7a30021eb10bd71d12 /src/soc/mediatek/mt8173/emi.c | |
| parent | 1c371572188a90ea16275460dd4ab6bf9966350b (diff) | |
| download | coreboot-55009af42c39f413c49503670ce9bc2858974962.tar.xz | |
Change all clrsetbits_leXX() to clrsetbitsXX()
This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.
This patch was created by running
sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'
across the codebase and cleaning up formatting a bit.
Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8173/emi.c')
| -rw-r--r-- | src/soc/mediatek/mt8173/emi.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c index be84668abe..f3ea7614e4 100644 --- a/src/soc/mediatek/mt8173/emi.c +++ b/src/soc/mediatek/mt8173/emi.c @@ -166,11 +166,11 @@ size_t sdram_size(void) static void init_4GB_mode(void) { if (sdram_size() == (size_t)4 * GiB) { - setbits_le32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT); - setbits_le32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN); + setbits32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT); + setbits32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN); } else { - clrbits_le32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT); - clrbits_le32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN); + clrbits32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT); + clrbits32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN); } } |