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| author | Yidi Lin <yidi.lin@mediatek.com> | 2016-02-04 17:26:48 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-03-12 09:14:33 +0100 |
| commit | c6d7dcc832521ad6e5d90ad82af384ec3d24aa09 (patch) | |
| tree | dd6c1ac29bca30d69b717d719b9aba05bee08007 /src/soc/mediatek/mt8173/emi.c | |
| parent | 9a64ec4dd239f2b757dff9effe3b10510034e62c (diff) | |
| download | coreboot-c6d7dcc832521ad6e5d90ad82af384ec3d24aa09.tar.xz | |
mediatek/mt8173: detect sdram size at runtime
Remove DRAM_SIZE_MB Kconfig setting and use sdram_size_mb() to detect
the DRAM size at runtime.
BUG=chrome-os-partner:49427
BRANCH=none
TEST=Boot to kernel
Change-Id: I0c3245db73335fb4f1c89c1debde715fc96ecba7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 00f6f2bbed0e7d23181337b9274191b31e73e223
Original-Change-Id: I409163fe527e966c184f28d7d9bbc809ae2308ed
Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com>
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327961
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331176
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13988
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8173/emi.c')
| -rw-r--r-- | src/soc/mediatek/mt8173/emi.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c index f6ef40f8f3..1ff4f23f10 100644 --- a/src/soc/mediatek/mt8173/emi.c +++ b/src/soc/mediatek/mt8173/emi.c @@ -127,6 +127,42 @@ static void init_dram(const struct mt8173_sdram_params *sdram_params) dramc_init(CHANNEL_B, sdram_params); } +size_t sdram_size(void) +{ + u32 value = read32(&emi_regs->emi_cona); + u32 bit_counter = 0; + + /* check if dual channel */ + if (value & CONA_DUAL_CH_EN) + bit_counter++; + + /* check if 32bit , 32 = 2^5*/ + if (value & CONA_32BIT_EN) + bit_counter += 5; + else + bit_counter += 4; + + /* check column address */ + /* 00 is 9 bits, 01 is 10 bits , 10 is 11 bits */ + bit_counter += ((value & COL_ADDR_BITS_MASK) >> COL_ADDR_BITS_SHIFT) + + 9; + + /* check if row address */ + /*00 is 13 bits , 01 is 14 bits , 10 is 15bits , 11 is 16 bits */ + bit_counter += ((value & ROW_ADDR_BITS_MASK) >> ROW_ADDR_BITS_SHIFT) + + 13; + + /* check if dual rank */ + if (value & CONA_DUAL_RANK_EN) + bit_counter++; + + /* add bank address bit, LPDDR3 is 8 banks =2^3 */ + bit_counter += 3; + + /*transfor bits to bytes */ + return ((size_t)1 << (bit_counter - 3)); +} + void mt_set_emi(const struct mt8173_sdram_params *sdram_params) { /* voltage info */ |