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authorKoro Chen <koro.chen@mediatek.com>2015-07-31 17:11:04 +0800
committerPatrick Georgi <pgeorgi@google.com>2016-01-22 19:37:33 +0100
commit64a6b9229a73a0577d7c738763d2d77d91bc0c49 (patch)
treea0f3f90c96a2d0819f5985281a1d395ea3716308 /src/soc/mediatek/mt8173/include
parent5d7c38ffa93b9713796bbccbf9c29cbacc1732d6 (diff)
downloadcoreboot-64a6b9229a73a0577d7c738763d2d77d91bc0c49.tar.xz
mediatek/mt8173: configure audio
BRANCH=none BUG=none TEST=build and verified pass on oak board Change-Id: I2680f6b87614362dffb27490bdeedf7125006c3f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc2bb9f5b461ec848df8aba07940b895401004f8 Original-Change-Id: I848468cec04a36659fbb4b898dff9368305d72ac Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292683 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13091 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8173/include')
-rw-r--r--src/soc/mediatek/mt8173/include/soc/mt6391.h67
1 files changed, 52 insertions, 15 deletions
diff --git a/src/soc/mediatek/mt8173/include/soc/mt6391.h b/src/soc/mediatek/mt8173/include/soc/mt6391.h
index f3224a0a5e..392ad634a7 100644
--- a/src/soc/mediatek/mt8173/include/soc/mt6391.h
+++ b/src/soc/mediatek/mt8173/include/soc/mt6391.h
@@ -262,21 +262,14 @@ enum{
};
enum ldo_power {
- LDO_VCAMD,
- LDO_VCAMIO,
- LDO_VCAMAF,
- LDO_VGP4,
- LDO_VGP5,
- LDO_VGP6,
- LDO_VTCXO,
- LDO_VA28,
- LDO_VCAMA,
- LDO_VIO28,
- LDO_VUSB,
- LDO_VMC,
- LDO_VMCH,
- LDO_VEMC3V3,
- LDO_VIBR,
+ LDO_VCAMD = 0, /* VGP1 */
+ LDO_VCAMIO = 1, /* VGP2 */
+ LDO_VCAMAF = 2, /* VGP3 */
+ LDO_VGP4 = 3,
+ LDO_VGP5 = 4,
+ LDO_VGP6 = 5,
+ /* special, not part of main register set */
+ LDO_VCAMA = 6,
};
enum ldo_voltage {
@@ -326,6 +319,50 @@ enum mt6391_pull_select {
MT6391_GPIO_PULL_UP = 1,
};
+enum {
+ MT6391_PMU_INT = 0,
+ MT6391_SRCVOLTEN = 1,
+ MT6391_SRCLKEN_PERI = 2,
+ MT6391_RTC32K_1V8 = 3,
+ MT6391_WRAP_EVENT = 4,
+ MT6391_SPI_CLK = 5,
+ MT6391_SPI_CSN = 6,
+ MT6391_SPI_MOSI = 7,
+ MT6391_SPI_MISO = 8,
+ MT6391_AUD_CLK_MOSI = 9,
+ MT6391_AUD_DAT_MISO = 10,
+ MT6391_AUD_DAT_MOSI = 11,
+ MT6391_KP_COL0 = 12,
+ MT6391_KP_COL1 = 13,
+ MT6391_KP_COL2 = 14,
+ MT6391_KP_COL3 = 15,
+ MT6391_KP_COL4 = 16,
+ MT6391_KP_COL5 = 17,
+ MT6391_KP_COL6 = 18,
+ MT6391_KP_COL7 = 19,
+ MT6391_KP_ROW0 = 20,
+ MT6391_KP_ROW1 = 21,
+ MT6391_KP_ROW2 = 22,
+ MT6391_KP_ROW3 = 23,
+ MT6391_KP_ROW4 = 24,
+ MT6391_KP_ROW5 = 25,
+ MT6391_KP_ROW6 = 26,
+ MT6391_KP_ROW7 = 27,
+ MT6391_VMSEL1 = 28,
+ MT6391_VMSEL2 = 29,
+ MT6391_PWM = 30,
+ MT6391_SCL0 = 31,
+ MT6391_SDA0 = 32,
+ MT6391_SCL1 = 33,
+ MT6391_SDA1 = 34,
+ MT6391_SCL2 = 35,
+ MT6391_SDA2 = 36,
+ MT6391_HDMISD = 37,
+ MT6391_HDMISCK = 38,
+ MT6391_HTPLG = 39,
+ MT6391_CEC = 40,
+};
+
/*
* PMIC GPIO Exported Function
*/