diff options
| author | Bayi Cheng <bayi.cheng@mediatek.com> | 2016-01-21 21:48:37 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-03-12 09:11:52 +0100 |
| commit | d8bb51eb4e00882259862129325aa7bf160f79c3 (patch) | |
| tree | 01e0ceae5f6951684328728302aaaab8a57647cf /src/soc/mediatek/mt8173/include | |
| parent | 5ffb6887c27d86215c5ffa603131ff9b1f0929ae (diff) | |
| download | coreboot-d8bb51eb4e00882259862129325aa7bf160f79c3.tar.xz | |
mediatek/mt8173: add NOR DMA read
BRANCH=none
BUG=none
TEST=boot oak to kernel on rev2
Change-Id: I368fcac1cf5e2261d00a34882a7341733ebd0732
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6ea0407f7273bc88613bc23a6fc4c41f9cca1adb
Original-Change-Id: Ic422e7265fdd35c573d8cd44280a1f7dc163a6db
Original-Signed-off-by: Bayi Cheng <bayi.cheng@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/323932
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13979
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8173/include')
| -rw-r--r-- | src/soc/mediatek/mt8173/include/soc/flash_controller.h | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/src/soc/mediatek/mt8173/include/soc/flash_controller.h b/src/soc/mediatek/mt8173/include/soc/flash_controller.h index 2527d6be6a..1d2ac32432 100644 --- a/src/soc/mediatek/mt8173/include/soc/flash_controller.h +++ b/src/soc/mediatek/mt8173/include/soc/flash_controller.h @@ -27,6 +27,7 @@ enum { SFLASHNAME_LENGTH = 16, SFLASH_WRITE_IN_PROGRESS = 1, SFLASH_COMMAND_ENABLE = 0x30, + SFLASH_DMA_ALIGN = 0x10, /* NOR flash controller commands */ SFLASH_RD_TRIGGER = 1 << 0, @@ -38,7 +39,11 @@ enum { /* NOR flash commands */ SFLASH_OP_WREN = 0x6, SECTOR_ERASE_CMD = 0x20, - SFLASH_UNPROTECTED = 0x0 + SFLASH_UNPROTECTED = 0x0, + /* DMA commands */ + SFLASH_DMA_TRIGGER = 1 << 0, + SFLASH_DMA_SW_RESET = 1 << 1, + SFLASH_DMA_WDLE_EN = 1 << 2 }; /* register Offset */ @@ -72,8 +77,14 @@ struct mt8173_nor_regs { u32 radr3; u32 read_dual; u32 delsel[3]; + u32 reserved[397]; + u32 cfg1_bri[2]; + u32 fdma_ctl; + u32 fdma_fadr; + u32 fdma_dadr; + u32 fdma_end_dadr; }; -check_member(mt8173_nor_regs, delsel[2], 0xD8); +check_member(mt8173_nor_regs, fdma_end_dadr, 0x724); static struct mt8173_nor_regs * const mt8173_nor = (void *)SFLASH_REG_BASE; struct spi_flash *mt8173_nor_flash_probe(struct spi_slave *spi); |