mediatek: Refactor PMIC wrapper code among similar SoCs

Refactor PMIC wrapper code which will be reused among similar SoCs.
Move reusable code into the common folder.

BUG=b:80501386
BRANCH=none
TEST=emerge-elm coreboot

Change-Id: I25acb6da49e72748d856804ef4f97e9ec3bef72d
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/29420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

2 files changed, 2 insertions, 92 deletions

diff --git a/src/soc/mediatek/mt8173/include/soc/mt6391.h b/src/soc/mediatek/mt8173/include/soc/mt6391.h
index 3091d06ed3..65b2f7ce8c 100644
--- a/src/soc/mediatek/mt8173/include/soc/mt6391.h
+++ b/src/soc/mediatek/mt8173/include/soc/mt6391.h
@@ -294,8 +294,6 @@ enum ldo_voltage {
  */
 int mt6391_configure_ca53_voltage(int uv);
 void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel);
-u32 mt6391_read(u16 reg, u32 mask, u32 shift);
-void mt6391_write(u16 reg, u16 val, u32 mask, u32 shift);
 void mt6391_enable_reset_when_ap_resets(void);
 void mt6391_init(void);
 
diff --git a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h
index 6807b13cbe..3687a2992d 100644
--- a/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h
+++ b/src/soc/mediatek/mt8173/include/soc/pmic_wrap.h
@@ -17,15 +17,10 @@
 #define SOC_MEDIATEK_MT8173_PMIC_WRAP_H
 
 #include <soc/addressmap.h>
+#include <soc/pmic_wrap_common.h>
 #include <types.h>
 
-/* external API */
-s32 pwrap_read(u16 adr, u16 *rdata);
-s32 pwrap_write(u16 adr, u16 wdata);
-s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check);
-s32 pwrap_init(void);
-
-static struct mt8173_pwrap_regs *const mt8173_pwrap = (void *)PMIC_WRAP_BASE;
+static struct mt8173_pwrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE;
 
 enum {
 	WACS2 = 1 << 4
@@ -44,12 +39,6 @@ enum {
 	PMIC_TOP_CKCON3      = PMIC_BASE + 0x01D4
 };
 
-/* timeout setting */
-enum {
-	TIMEOUT_READ_US        = 255,
-	TIMEOUT_WAIT_IDLE_US   = 255
-};
-
 /* PMIC_WRAP registers */
 struct mt8173_pwrap_regs {
 	u32 mux_sel;
@@ -136,36 +125,6 @@ struct mt8173_pwrap_regs {
 
 check_member(mt8173_pwrap_regs, dcm_dbc_prd, 0x148);
 
-enum {
-	RDATA_WACS_RDATA_SHIFT = 0,
-	RDATA_WACS_FSM_SHIFT   = 16,
-	RDATA_WACS_REQ_SHIFT   = 19,
-	RDATA_SYNC_IDLE_SHIFT,
-	RDATA_INIT_DONE_SHIFT,
-	RDATA_SYS_IDLE_SHIFT,
-};
-
-enum {
-	RDATA_WACS_RDATA_MASK = 0xffff,
-	RDATA_WACS_FSM_MASK   = 0x7,
-	RDATA_WACS_REQ_MASK   = 0x1,
-	RDATA_SYNC_IDLE_MASK  = 0x1,
-	RDATA_INIT_DONE_MASK  = 0x1,
-	RDATA_SYS_IDLE_MASK   = 0x1,
-};
-
-/* WACS_FSM */
-enum {
-	WACS_FSM_IDLE     = 0x00,
-	WACS_FSM_REQ      = 0x02,
-	WACS_FSM_WFDLE    = 0x04, /* wait for dle, wait for read data done */
-	WACS_FSM_WFVLDCLR = 0x06, /* finish read data, wait for valid flag
-				   * clearing */
-	WACS_INIT_DONE    = 0x01,
-	WACS_SYNC_IDLE    = 0x01,
-	WACS_SYNC_BUSY    = 0x00
-};
-
 /* dewrapper regsister */
 enum {
 	DEW_EVENT_OUT_EN   = DEW_BASE + 0x0,
@@ -195,57 +154,10 @@ enum {
 	DEW_CIPHER_IV5     = DEW_BASE + 0x30
 };
 
-/* dewrapper defaule value */
-enum {
-	DEFAULT_VALUE_READ_TEST  = 0x5aa5,
-	WRITE_TEST_VALUE         = 0xa55a
-};
-
 enum pmic_regck {
 	REG_CLOCK_18MHZ,
 	REG_CLOCK_26MHZ,
 	REG_CLOCK_SAFE_MODE
 };
 
-/* manual commnd */
-enum {
-	OP_WR    = 0x1,
-	OP_CSH   = 0x0,
-	OP_CSL   = 0x1,
-	OP_OUTS  = 0x8,
-	OP_OUTD  = 0x9,
-	OP_INS   = 0xC,
-	OP_IND   = 0xD
-};
-
-/* error information flag */
-enum {
-	E_PWR_INVALID_ARG             = 1,
-	E_PWR_INVALID_RW              = 2,
-	E_PWR_INVALID_ADDR            = 3,
-	E_PWR_INVALID_WDAT            = 4,
-	E_PWR_INVALID_OP_MANUAL       = 5,
-	E_PWR_NOT_IDLE_STATE          = 6,
-	E_PWR_NOT_INIT_DONE           = 7,
-	E_PWR_NOT_INIT_DONE_READ      = 8,
-	E_PWR_WAIT_IDLE_TIMEOUT       = 9,
-	E_PWR_WAIT_IDLE_TIMEOUT_READ  = 10,
-	E_PWR_INIT_SIDLY_FAIL         = 11,
-	E_PWR_RESET_TIMEOUT           = 12,
-	E_PWR_TIMEOUT                 = 13,
-	E_PWR_INIT_RESET_SPI          = 20,
-	E_PWR_INIT_SIDLY              = 21,
-	E_PWR_INIT_REG_CLOCK          = 22,
-	E_PWR_INIT_ENABLE_PMIC        = 23,
-	E_PWR_INIT_DIO                = 24,
-	E_PWR_INIT_CIPHER             = 25,
-	E_PWR_INIT_WRITE_TEST         = 26,
-	E_PWR_INIT_ENABLE_CRC         = 27,
-	E_PWR_INIT_ENABLE_DEWRAP      = 28,
-	E_PWR_INIT_ENABLE_EVENT       = 29,
-	E_PWR_READ_TEST_FAIL          = 30,
-	E_PWR_WRITE_TEST_FAIL         = 31,
-	E_PWR_SWITCH_DIO              = 32
-};
-
 #endif /* SOC_MEDIATEK_MT8173_PMIC_WRAP_H */