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| author | Yidi Lin <yidi.lin@mediatek.com> | 2016-02-04 17:26:48 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-03-12 09:14:33 +0100 |
| commit | c6d7dcc832521ad6e5d90ad82af384ec3d24aa09 (patch) | |
| tree | dd6c1ac29bca30d69b717d719b9aba05bee08007 /src/soc/mediatek/mt8173/include | |
| parent | 9a64ec4dd239f2b757dff9effe3b10510034e62c (diff) | |
| download | coreboot-c6d7dcc832521ad6e5d90ad82af384ec3d24aa09.tar.xz | |
mediatek/mt8173: detect sdram size at runtime
Remove DRAM_SIZE_MB Kconfig setting and use sdram_size_mb() to detect
the DRAM size at runtime.
BUG=chrome-os-partner:49427
BRANCH=none
TEST=Boot to kernel
Change-Id: I0c3245db73335fb4f1c89c1debde715fc96ecba7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 00f6f2bbed0e7d23181337b9274191b31e73e223
Original-Change-Id: I409163fe527e966c184f28d7d9bbc809ae2308ed
Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com>
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327961
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331176
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13988
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8173/include')
| -rw-r--r-- | src/soc/mediatek/mt8173/include/soc/emi.h | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8173/include/soc/emi.h b/src/soc/mediatek/mt8173/include/soc/emi.h index d3a2aeec9c..959e1c93af 100644 --- a/src/soc/mediatek/mt8173/include/soc/emi.h +++ b/src/soc/mediatek/mt8173/include/soc/emi.h @@ -18,6 +18,7 @@ #include <soc/dramc_common.h> #include <stdint.h> +#include <types.h> /* DDR type */ enum ram_type { @@ -124,6 +125,17 @@ struct mt8173_mrs_params { u32 mrs_63; }; +enum { + /* CONA = 0x000 */ + CONA_DUAL_CH_EN = BIT(0), + CONA_32BIT_EN = BIT(1), + CONA_DUAL_RANK_EN = BIT(17), + COL_ADDR_BITS_SHIFT = 4, + COL_ADDR_BITS_MASK = 3 << COL_ADDR_BITS_SHIFT, + ROW_ADDR_BITS_SHIFT = 12, + ROW_ADDR_BITS_MASK = 3 << ROW_ADDR_BITS_SHIFT +}; + struct mt8173_sdram_params { struct mt8173_calib_params calib_params; struct mt8173_timing_params ac_timing; @@ -136,5 +148,5 @@ struct mt8173_sdram_params { void mt_set_emi(const struct mt8173_sdram_params *sdram_params); void mt_mem_init(const struct mt8173_sdram_params *sdram_params); const struct mt8173_sdram_params *get_sdram_config(void); - +size_t sdram_size(void); #endif |