diff options
| author | Yidi Lin <yidi.lin@mediatek.com> | 2016-01-29 17:25:03 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-03-12 09:12:13 +0100 |
| commit | a622f28cb249c9d88751ce2694c83a62c25c221e (patch) | |
| tree | a16fc8f7c5c83dfb118ee3c5b56bfaee034ca7ae /src/soc/mediatek/mt8173/pll.c | |
| parent | d8bb51eb4e00882259862129325aa7bf160f79c3 (diff) | |
| download | coreboot-a622f28cb249c9d88751ce2694c83a62c25c221e.tar.xz | |
mediatek/mt8173: pll: raising the CPU core frequency
Runs the LITTLE core at highest freqency to speed up the boot time.
Set Vproc to 1.125V and set the freqency to 1.6Ghz for backward
compatibility. (The highest frequency for the IC before E3 is 1.6Ghz.)
BRANCH=none
BUG=chrome-os-partner:47422
TEST=flash the bootloader and measure the boottime by cbmem result
Change-Id: Id0b906bf34ac534667eb6e8f576e30942ceb923e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5fc38548d158158f07cded8cfc8ea5a0a7952161
Original-Change-Id: I62af26c13d98211974243100c581abcb5408fd63
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/324685
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13980
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8173/pll.c')
| -rw-r--r-- | src/soc/mediatek/mt8173/pll.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index d54538d91d..1366bb5888 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -467,8 +467,6 @@ void mt_pll_post_init(void) clrbits_le32(&mt8173_infracfg->top_ckdiv1, 0x3ff); /* select ARMPLL */ - /* TODO: possibly raise ARMPLL frequency here */ - /* NOTICE: raise Vproc voltage before raise ARMPLL frequency */ write32(&mt8173_infracfg->top_ckmuxsel, (1 << 2) | 1); } @@ -506,6 +504,10 @@ void mt_pll_set_aud_div(u32 rate) } } +void mt_pll_raise_ca53_freq(u32 freq) { + pll_set_rate(&plls[APMIXED_ARMCA7PLL], freq); /* freq in Hz */ +} + void mt_mem_pll_config_pre(const struct mt8173_sdram_params *sdram_params) { u32 mpll_sdm_pcw_20_0 = 0xF13B1; |