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authorPeter Kao <peter.kao@mediatek.com>2015-07-31 17:11:14 +0800
committerPatrick Georgi <pgeorgi@google.com>2016-03-12 09:00:21 +0100
commitda1e02a3a0cd8de244a03cc84d5ecc9663e5e694 (patch)
tree561d900efe1632f802de2eee84ff11d6f4465ed5 /src/soc/mediatek/mt8173/pll.c
parentb74a2eca80deed3e7d21ba1123c2b986abcfcc10 (diff)
downloadcoreboot-da1e02a3a0cd8de244a03cc84d5ecc9663e5e694.tar.xz
mediatek/mt8173: Add EMI driver, DRAM initialization
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I6b05898de2d0022e0de7b18f1db3c3e9c06d8135 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b614eeb1bba5660438c214e82225832809caca8e Original-Change-Id: I0f7b0a426dae1548b34114a024c92befdf6002f6 Original-Signed-off-by: Peter Kao <peter.kao@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292692 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13105 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8173/pll.c')
-rw-r--r--src/soc/mediatek/mt8173/pll.c26
1 files changed, 26 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c
index 3faf7859a7..d54538d91d 100644
--- a/src/soc/mediatek/mt8173/pll.c
+++ b/src/soc/mediatek/mt8173/pll.c
@@ -505,3 +505,29 @@ void mt_pll_set_aud_div(u32 rate)
7 << 28);
}
}
+
+void mt_mem_pll_config_pre(const struct mt8173_sdram_params *sdram_params)
+{
+ u32 mpll_sdm_pcw_20_0 = 0xF13B1;
+
+ /* disable MPLL for adjusting memory clk frequency */
+ clrbits_le32(&mt8173_apmixed->mpll_con0, BIT(0));
+ /* MPLL configuration: mode selection */
+ setbits_le32(&mt8173_apmixed->mpll_con0, BIT(16));
+ clrbits_le32(&mt8173_apmixed->mpll_con0, 0x7 << 4);
+ clrbits_le32(&mt8173_apmixed->pll_test_con0, 1 << 31);
+ /* set RG_MPLL_SDM_PCW for feedback divide ratio */
+ clrsetbits_le32(&mt8173_apmixed->mpll_con1, 0x1fffff, mpll_sdm_pcw_20_0);
+}
+
+void mt_mem_pll_config_post(void)
+{
+ /* power up sequence starts: enable MPLL */
+ setbits_le32(&mt8173_apmixed->mpll_con0, BIT(0));
+}
+
+void mt_mem_pll_mux(void)
+{
+ /* CLK_CFG_0 */
+ mux_set_sel(&muxes[TOP_MEM_SEL], 1); /* 1: dmpll_ck */
+}