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authorTristan Shieh <tristan.shieh@mediatek.com>2018-11-01 18:01:50 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-11-16 09:51:54 +0000
commitab1b83d5a4aa7775154ef53782f68314610b53d5 (patch)
tree0f20c7f1b604ec6ff5b45efa443c8028f7395ebe /src/soc/mediatek/mt8173/rtc.c
parentd3d0f07fd58b4037a2f4a13f3fcbe7947ef1ad5d (diff)
downloadcoreboot-ab1b83d5a4aa7775154ef53782f68314610b53d5.tar.xz
mediatek: Refactor PMIC wrapper code among similar SoCs
Refactor PMIC wrapper code which will be reused among similar SoCs. Move reusable code into the common folder. BUG=b:80501386 BRANCH=none TEST=emerge-elm coreboot Change-Id: I25acb6da49e72748d856804ef4f97e9ec3bef72d Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/29420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8173/rtc.c')
-rw-r--r--src/soc/mediatek/mt8173/rtc.c23
1 files changed, 12 insertions, 11 deletions
diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c
index 4d2cad42b9..153e9b4249 100644
--- a/src/soc/mediatek/mt8173/rtc.c
+++ b/src/soc/mediatek/mt8173/rtc.c
@@ -102,7 +102,7 @@ static void rtc_xosc_write(u16 val)
pwrap_write(RTC_OSC32CON, val);
udelay(200);
- mt6391_write(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD, 0, 0);
+ pwrap_write_field(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD, 0, 0);
write_trigger();
}
@@ -175,15 +175,15 @@ static void rtc_osc_init(void)
/* low power detect setting */
static int rtc_lpd_init(void)
{
- mt6391_write(RTC_CON, RTC_CON_LPEN, RTC_CON_LPRST, 0);
+ pwrap_write_field(RTC_CON, RTC_CON_LPEN, RTC_CON_LPRST, 0);
if (!write_trigger())
return 0;
- mt6391_write(RTC_CON, RTC_CON_LPRST, 0, 0);
+ pwrap_write_field(RTC_CON, RTC_CON_LPRST, 0, 0);
if (!write_trigger())
return 0;
- mt6391_write(RTC_CON, 0, RTC_CON_LPRST, 0);
+ pwrap_write_field(RTC_CON, 0, RTC_CON_LPRST, 0);
if (!write_trigger())
return 0;
@@ -203,7 +203,7 @@ static int rtc_init(u8 recover)
/* Use SW to detect 32K mode instead of HW */
if (recover)
- mt6391_write(PMIC_RG_CHRSTATUS, 0x4, 0x1, 9);
+ pwrap_write_field(PMIC_RG_CHRSTATUS, 0x4, 0x1, 9);
rtc_xosc_write(0x3);
@@ -217,7 +217,7 @@ static int rtc_init(u8 recover)
return 0;
if (recover)
- mt6391_write(PMIC_RG_CHRSTATUS, 0, 0x4, 9);
+ pwrap_write_field(PMIC_RG_CHRSTATUS, 0, 0x4, 9);
rtc_xosc_write(0);
@@ -243,17 +243,17 @@ static void rtc_bbpu_power_on(void)
/* enable DCXO to transform external 32KHz clock to 26MHz clock
directly sent to SoC */
- mt6391_write(PMIC_RG_DCXO_FORCE_MODE1, BIT(11), 0, 0);
- mt6391_write(PMIC_RG_DCXO_POR2_CON3,
+ pwrap_write_field(PMIC_RG_DCXO_FORCE_MODE1, BIT(11), 0, 0);
+ pwrap_write_field(PMIC_RG_DCXO_POR2_CON3,
BIT(8) | BIT(9) | BIT(10) | BIT(11), 0, 0);
- mt6391_write(PMIC_RG_DCXO_CON2,
+ pwrap_write_field(PMIC_RG_DCXO_CON2,
BIT(1) | BIT(3) | BIT(5) | BIT(6), 0, 0);
pwrap_read(RTC_BBPU, &bbpu);
printk(BIOS_INFO, "[RTC] %s done BBPU=%#x\n", __func__, bbpu);
/* detect hw clock done,close RG_RTC_75K_PDN for low power setting. */
- mt6391_write(PMIC_RG_TOP_CKPDN2, 0x1, 0, 14);
+ pwrap_write_field(PMIC_RG_TOP_CKPDN2, 0x1, 0, 14);
}
static u8 rtc_check_state(void)
@@ -293,7 +293,8 @@ void rtc_boot(void)
switch (rtc_check_state()) {
case RTC_STATE_REBOOT:
- mt6391_write(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD, 0, 0);
+ pwrap_write_field(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD, 0,
+ 0);
write_trigger();
rtc_osc_init();
break;