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authorMengqi Zhang <Mengqi.Zhang@mediatek.com>2019-04-24 11:11:52 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-06-21 08:38:41 +0000
commit026be3d76f3934eb901485acd98e0d84f137068f (patch)
treec269b874ad1fccd60889cc0fac94dd1f746608a7 /src/soc/mediatek/mt8173
parent89b1753c2289edacca05ef46e840f212f2a3025d (diff)
downloadcoreboot-026be3d76f3934eb901485acd98e0d84f137068f.tar.xz
mediatek: Add SPI tick_dly setting
Add spi tick_dly setting for high-speed spi xfer. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; emerge-elm coreboot Change-Id: Ie49fc3efe2a4a6dcdf2a2fc4c91b47e35d4f086e Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8173')
-rw-r--r--src/soc/mediatek/mt8173/include/soc/spi.h5
-rw-r--r--src/soc/mediatek/mt8173/spi.c7
2 files changed, 10 insertions, 2 deletions
diff --git a/src/soc/mediatek/mt8173/include/soc/spi.h b/src/soc/mediatek/mt8173/include/soc/spi.h
index aaef3aa25c..58bf517f9d 100644
--- a/src/soc/mediatek/mt8173/include/soc/spi.h
+++ b/src/soc/mediatek/mt8173/include/soc/spi.h
@@ -43,4 +43,9 @@ enum {
SPI_CFG0_CS_SETUP_SHIFT = 24,
};
+enum {
+ SPI_CFG1_TICK_DLY_SHIFT = 30,
+ SPI_CFG1_TICK_DLY_MASK = 0x3 << SPI_CFG1_TICK_DLY_SHIFT,
+};
+
#endif
diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c
index 0cc8377ff4..d0094418b8 100644
--- a/src/soc/mediatek/mt8173/spi.c
+++ b/src/soc/mediatek/mt8173/spi.c
@@ -38,14 +38,17 @@ void mtk_spi_set_gpio_pinmux(unsigned int bus,
gpio_set_mode(GPIO(MSDC2_CMD), PAD_MSDC2_CMD_FUNC_SPI_CS_1);
}
-void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks)
+void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks,
+ unsigned int tick_dly)
{
write32(&regs->spi_cfg0_reg,
((sck_ticks - 1) << SPI_CFG0_SCK_HIGH_SHIFT) |
((sck_ticks - 1) << SPI_CFG0_SCK_LOW_SHIFT) |
((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) |
((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT));
- clrsetbits_le32(&regs->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK,
+ clrsetbits_le32(&regs->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK |
+ SPI_CFG1_TICK_DLY_MASK,
+ (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) |
((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT));
}