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authorHung-Te Lin <hungte@chromium.org>2019-08-08 06:28:43 +0800
committerJulius Werner <jwerner@chromium.org>2019-08-13 02:37:18 +0000
commit302dddf0f48acce1c00ae04606b0bf56c7da3f9d (patch)
treefb96c4bdf5e7ef7724763a49af01d1513d07e95a /src/soc/mediatek/mt8173
parent61e346624a2c8b7e3de5313f2f4bfa2d4359e660 (diff)
downloadcoreboot-302dddf0f48acce1c00ae04606b0bf56c7da3f9d.tar.xz
soc/mediatek: dsi: Refactor MIPI TX configuration
The only platform-specific difference in mtk_dsi_phy_clk_setting is how to configure MIPI TX because those registers (and logic) are quite different across different SOCs. The calculation of data rate is actually the same so we should isolate it and move to common, and rename mtk_dsi_phy_clk_setting to a better name as mtk_dsi_configure_mipi_tx. BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots Change-Id: I894dc2c4c053267debf5a58313b2bb489bcf5f3a Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8173')
-rw-r--r--src/soc/mediatek/mt8173/dsi.c30
-rw-r--r--src/soc/mediatek/mt8173/include/soc/dsi.h5
2 files changed, 11 insertions, 24 deletions
diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c
index 25030c621c..2e4a4bd58a 100644
--- a/src/soc/mediatek/mt8173/dsi.c
+++ b/src/soc/mediatek/mt8173/dsi.c
@@ -13,20 +13,19 @@
* GNU General Public License for more details.
*/
+#include <assert.h>
#include <device/mmio.h>
#include <console/console.h>
#include <delay.h>
-#include <edid.h>
#include <soc/dsi.h>
#include <timer.h>
-int mtk_dsi_phy_clk_setting(u32 bits_per_pixel, u32 lanes,
- const struct edid *edid)
+void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes)
{
u32 txdiv0, txdiv1;
u64 pcw;
u32 reg;
- int i, data_rate, mipi_tx_rate;
+ int i;
reg = read32(&mipi_tx0->dsi_bg_con);
@@ -52,16 +51,6 @@ int mtk_dsi_phy_clk_setting(u32 bits_per_pixel, u32 lanes,
clrbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN);
- /**
- * data_rate = pixel_clock / 1000 * bits_per_pixel * mipi_ratio / lanes
- * pixel_clock unit is Khz, data_rata unit is MHz, so need divide 1000.
- * mipi_ratio is mipi clk coefficient for balance the pixel clk in mipi.
- * we set mipi_ratio is 1.02.
- */
- data_rate = edid->mode.pixel_clock * 102 * bits_per_pixel /
- (lanes * 1000 * 100);
- mipi_tx_rate = data_rate;
-
if (data_rate > 500) {
txdiv0 = 0;
txdiv1 = 0;
@@ -74,16 +63,11 @@ int mtk_dsi_phy_clk_setting(u32 bits_per_pixel, u32 lanes,
} else if (data_rate >= 62) {
txdiv0 = 2;
txdiv1 = 1;
- } else if (data_rate >= 50) {
+ } else {
+ /* MIN = 50 */
+ assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ);
txdiv0 = 2;
txdiv1 = 2;
- } else {
- printk(BIOS_ERR, "data rate (%u) must be >=50. "
- "Please check pixel clock (%u), bits per pixel (%u), "
- "and number of lanes (%u)\n",
- data_rate, edid->mode.pixel_clock, bits_per_pixel,
- lanes);
- return -1;
}
clrsetbits_le32(&mipi_tx0->dsi_pll_con0,
@@ -115,8 +99,6 @@ int mtk_dsi_phy_clk_setting(u32 bits_per_pixel, u32 lanes,
clrbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN);
clrbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN);
-
- return mipi_tx_rate;
}
void mtk_dsi_reset(void)
diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h
index f7c622745d..99c51e62ff 100644
--- a/src/soc/mediatek/mt8173/include/soc/dsi.h
+++ b/src/soc/mediatek/mt8173/include/soc/dsi.h
@@ -18,6 +18,11 @@
#include <soc/dsi_common.h>
+/* DSI features */
+#define MTK_DSI_MIPI_RATIO_NUMERATOR 102
+#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100
+#define MTK_DSI_DATA_RATE_MIN_MHZ 50
+
/* MIPITX is SOC specific and cannot live in common. */
/* MIPITX_REG */