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authorYu-Ping Wu <yupingso@chromium.org>2020-02-11 18:33:57 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-02-17 15:38:08 +0000
commit443fbd70495404a99a17be990518c237f3654227 (patch)
tree23c1ac2b90b0b41b16055ffcfd5ed3621bcf27de /src/soc/mediatek/mt8173
parentfa36d0b79fb9fdc9747bb653398c1893eb7221c8 (diff)
downloadcoreboot-443fbd70495404a99a17be990518c237f3654227.tar.xz
soc/mediatek: dsi: Increase pcw precision
When configuring MIPI DSI Tx, the value of pcw was calculated from data rate in MHz, leading to loss of precision. This patch changes to use data rate in Hz for the calculation so that the resulting value should be consistent with the one in kernel (CL:1786327). In addition, change the type of data rate to u32, and calculation of data rate from pixel clock is changed to use DIV_ROUND_UP for consistency with kernel (CL:1761843). Also remove unused variable txdiv. BRANCH=kukui BUG=b:149051882 TEST=emerge-jacuzzi coreboot TEST=No scrolling issue on Juniper AUO and InnoLux panels Change-Id: I23220d446833b956431006027bbc8cb20fc696a5 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38827 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8173')
-rw-r--r--src/soc/mediatek/mt8173/dsi.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c
index dae23f5a0c..48bfbef1a5 100644
--- a/src/soc/mediatek/mt8173/dsi.c
+++ b/src/soc/mediatek/mt8173/dsi.c
@@ -20,7 +20,7 @@
#include <soc/dsi.h>
#include <timer.h>
-void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes)
+void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes)
{
u32 txdiv0, txdiv1;
u64 pcw;
@@ -51,21 +51,21 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes)
clrbits32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN);
- if (data_rate > 500) {
+ if (data_rate > 500 * MHz) {
txdiv0 = 0;
txdiv1 = 0;
- } else if (data_rate >= 250) {
+ } else if (data_rate >= 250 * MHz) {
txdiv0 = 1;
txdiv1 = 0;
- } else if (data_rate >= 125) {
+ } else if (data_rate >= 125 * MHz) {
txdiv0 = 2;
txdiv1 = 0;
- } else if (data_rate >= 62) {
+ } else if (data_rate >= 62 * MHz) {
txdiv0 = 2;
txdiv1 = 1;
} else {
/* MIN = 50 */
- assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ);
+ assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ * MHz);
txdiv0 = 2;
txdiv1 = 2;
}
@@ -83,7 +83,7 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes)
* Ref_clk is 26MHz
*/
pcw = (u64)(data_rate * (1 << txdiv0) * (1 << txdiv1)) << 24;
- pcw /= 13;
+ pcw /= 13 * MHz;
write32(&mipi_tx0->dsi_pll_con2, pcw);
setbits32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN);