diff options
author | Tristan Shieh <tristan.shieh@mediatek.com> | 2019-04-26 11:58:30 +0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-29 12:27:24 +0000 |
commit | 3d96f6040901dea0b83939a9bceb49babe91c614 (patch) | |
tree | ba65b5e2689e71bcab711fa5503bdc4e4dafc0af /src/soc/mediatek/mt8173 | |
parent | d95425c51a6cd11a9a22d007afb66ef841359e96 (diff) | |
download | coreboot-3d96f6040901dea0b83939a9bceb49babe91c614.tar.xz |
mediatek: Add function to raise the CPU frequency
Implement mt_pll_raise_ca53_freq() in MT8183 to raise the CPU frequency.
Move the function declaration to common header.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui
Change-Id: Ide8d767486d68177fa2bfbcc5b559879eca1bcda
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8173')
-rw-r--r-- | src/soc/mediatek/mt8173/include/soc/pll.h | 1 | ||||
-rw-r--r-- | src/soc/mediatek/mt8173/pll.c | 3 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/mediatek/mt8173/include/soc/pll.h b/src/soc/mediatek/mt8173/include/soc/pll.h index 4106d2a924..480ffbfb2d 100644 --- a/src/soc/mediatek/mt8173/include/soc/pll.h +++ b/src/soc/mediatek/mt8173/include/soc/pll.h @@ -292,7 +292,6 @@ enum { void mt_pll_post_init(void); void mt_pll_set_aud_div(u32 rate); void mt_pll_enable_ssusb_clk(void); -void mt_pll_raise_ca53_freq(u32 freq); void mt_mem_pll_set_clk_cfg(void); void mt_mem_pll_config_pre(const struct mt8173_sdram_params *sdram_params); void mt_mem_pll_config_post(void); diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index c59fa3f528..7eb12b1282 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -432,7 +432,8 @@ void mt_pll_set_aud_div(u32 rate) } } -void mt_pll_raise_ca53_freq(u32 freq) { +void mt_pll_raise_ca53_freq(u32 freq) +{ pll_set_rate(&plls[APMIXED_ARMCA7PLL], freq); /* freq in Hz */ } |