mediatek: Move uart, timer and cbmem code to a common directory.

This patch moves uart, timer and cbmem code which can be reused into a
common directory under soc/mediatek.

BUG=b:80501386
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
     of the patches applied) and Elm platform

Change-Id: I5210149b324947ee90f1a481b42f0e2e1f7cfc25
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

5 files changed, 11 insertions, 322 deletions

diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc
index 3aa463a928..3bb0ae0b31 100644
--- a/src/soc/mediatek/mt8173/Makefile.inc
+++ b/src/soc/mediatek/mt8173/Makefile.inc
@@ -20,11 +20,11 @@ bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c
 bootblock-y += i2c.c
 bootblock-y += pll.c
 bootblock-y += spi.c
-bootblock-y += common_timer.c
+bootblock-y += ../common/timer.c
 bootblock-y += timer.c
 
 ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
-bootblock-$(CONFIG_DRIVERS_UART) += uart.c
+bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c
 endif
 
 bootblock-y += gpio.c gpio_init.c pmic_wrap.c mt6391.c
@@ -36,9 +36,9 @@ bootblock-y += mmu_operations.c
 verstage-y += i2c.c
 verstage-y += spi.c
 
-verstage-$(CONFIG_DRIVERS_UART) += uart.c
+verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
 
-verstage-y += common_timer.c
+verstage-y += ../common/timer.c
 verstage-y += timer.c
 verstage-y += wdt.c
 verstage-$(CONFIG_SPI_FLASH) += flash_controller.c
@@ -48,11 +48,11 @@ verstage-y += gpio.c
 
 romstage-$(CONFIG_SPI_FLASH) += flash_controller.c
 romstage-y += pll.c
-romstage-y += common_timer.c
+romstage-y += ../common/timer.c
 romstage-y += timer.c
 
-romstage-$(CONFIG_DRIVERS_UART) += uart.c
-romstage-y += cbmem.c
+romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
+romstage-y += ../common/cbmem.c
 romstage-y += spi.c
 romstage-y += gpio.c
 romstage-y += pmic_wrap.c mt6391.c
@@ -63,13 +63,13 @@ romstage-y += rtc.c
 
 ################################################################################
 
-ramstage-y += cbmem.c emi.c
+ramstage-y += ../common/cbmem.c emi.c
 ramstage-y += spi.c
 ramstage-$(CONFIG_SPI_FLASH) += flash_controller.c
 ramstage-y += soc.c mtcmos.c
-ramstage-y += common_timer.c
+ramstage-y += ../common/timer.c
 ramstage-y += timer.c
-ramstage-$(CONFIG_DRIVERS_UART) += uart.c
+ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
 ramstage-y += pmic_wrap.c mt6391.c i2c.c
 ramstage-y += mt6311.c
 ramstage-y += da9212.c
@@ -94,5 +94,6 @@ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
 	./util/mtkheader/gen-bl-img.py mt8173 sf $< $@
 
 CPPFLAGS_common += -Isrc/soc/mediatek/mt8173/include
+CPPFLAGS_common += -Isrc/soc/mediatek/common/include
 
 endif
diff --git a/src/soc/mediatek/mt8173/cbmem.c b/src/soc/mediatek/mt8173/cbmem.c
deleted file mode 100644
index 31ea1baef4..0000000000
--- a/src/soc/mediatek/mt8173/cbmem.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 MediaTek Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <cbmem.h>
-#include <stddef.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <soc/emi.h>
-
-#define MAX_DRAM_ADDRESS ((uintptr_t)4 * GiB)
-
-void *cbmem_top(void)
-{
-	return (void *)min((uintptr_t)_dram + sdram_size(), MAX_DRAM_ADDRESS);
-}
diff --git a/src/soc/mediatek/mt8173/common_timer.c b/src/soc/mediatek/mt8173/common_timer.c
deleted file mode 100644
index 6e4315c7cf..0000000000
--- a/src/soc/mediatek/mt8173/common_timer.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2018 MediaTek Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <compiler.h>
-#include <console/console.h>
-#include <timer.h>
-#include <delay.h>
-#include <thread.h>
-
-#include <soc/addressmap.h>
-#include <soc/timer.h>
-
-static struct mtk_gpt_regs *const mtk_gpt = (void *)GPT_BASE;
-
-__weak void timer_prepare(void) { /* do nothing */ }
-
-void timer_monotonic_get(struct mono_time *mt)
-{
-	mono_time_set_usecs(mt, read32(&mtk_gpt->gpt4_cnt) / GPT4_MHZ);
-}
-
-void init_timer(void)
-{
-	timer_prepare();
-
-	/* Disable GPT4 and clear the counter */
-	clrbits_le32(&mtk_gpt->gpt4_con, GPT_CON_EN);
-	setbits_le32(&mtk_gpt->gpt4_con, GPT_CON_CLR);
-
-	/* Set clock source to system clock and set clock divider to 1 */
-	write32(&mtk_gpt->gpt4_clk, GPT_SYS_CLK | GPT_CLK_DIV1);
-	/* Set operation mode to FREERUN mode and enable GTP4 */
-	write32(&mtk_gpt->gpt4_con, GPT_CON_EN | GPT_MODE_FREERUN);
-}
diff --git a/src/soc/mediatek/mt8173/include/soc/timer.h b/src/soc/mediatek/mt8173/include/soc/timer.h
deleted file mode 100644
index e876971d06..0000000000
--- a/src/soc/mediatek/mt8173/include/soc/timer.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 MediaTek Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef SOC_MEDIATEK_COMMON_TIMER_H
-#define SOC_MEDIATEK_COMMON_TIMER_H
-
-#include <soc/addressmap.h>
-#include <types.h>
-
-#define GPT4_MHZ	13
-
-struct mtk_gpt_regs {
-	u32 reserved[16];
-	u32 gpt4_con;
-	u32 gpt4_clk;
-	u32 gpt4_cnt;
-};
-
-check_member(mtk_gpt_regs, gpt4_con, 0x0040);
-check_member(mtk_gpt_regs, gpt4_clk, 0x0044);
-check_member(mtk_gpt_regs, gpt4_cnt, 0x0048);
-
-enum {
-	GPT_CON_EN        = 0x01,
-	GPT_CON_CLR       = 0x02,
-	GPT_MODE_FREERUN  = 0x30,
-	GPT_SYS_CLK       = 0x00,
-	GPT_CLK_DIV1      = 0x00,
-};
-
-/*
- * This is defined as weak no-ops that can be overridden by legacy SOCs. Some
- * legacy SOCs need specific settings before init timer. And we expect future
- * SOCs will not need it.
- */
-void timer_prepare(void);
-
-#endif
diff --git a/src/soc/mediatek/mt8173/uart.c b/src/soc/mediatek/mt8173/uart.c
deleted file mode 100644
index 961e3eb9be..0000000000
--- a/src/soc/mediatek/mt8173/uart.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 MediaTek Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/console.h>	/* for __console definition */
-#include <console/uart.h>
-#include <drivers/uart/uart8250reg.h>
-#include <stdint.h>
-#include <compiler.h>
-
-#include <soc/addressmap.h>
-
-struct mtk_uart {
-	union {
-		uint32_t thr;	/* Transmit holding register. */
-		uint32_t rbr;	/* Receive buffer register. */
-		uint32_t dll;	/* Divisor latch lsb. */
-	};
-	union {
-		uint32_t ier;	/* Interrupt enable register. */
-		uint32_t dlm;	/* Divisor latch msb. */
-	};
-	union {
-		uint32_t iir;	/* Interrupt identification register. */
-		uint32_t fcr;	/* FIFO control register. */
-		uint32_t efr;	/* Enhanced feature register. */
-	};
-	uint32_t lcr;		/* Line control register. */
-	union {
-		uint32_t mcr;	/* Modem control register. */
-		uint32_t xn1;	/* XON1 */
-	};
-	union {
-		uint32_t lsr;	/* Line status register. */
-		uint32_t xn2;	/* XON2 */
-	};
-	union {
-		uint32_t msr;	/* Modem status register. */
-		uint32_t xf1;	/* XOFF1 */
-	};
-	union {
-		uint32_t scr;	/* Scratch register. */
-		uint32_t xf2;	/* XOFF2 */
-	};
-	uint32_t autobaud_en;	/* Enable auto baudrate. */
-	uint32_t highspeed;	/* High speed UART. */
-} __packed;
-
-/* Peripheral Reset and Power Down registers */
-struct mtk_peri_globalcon {
-	uint32_t rst0;
-	uint32_t rst1;
-	uint32_t pdn0_set;
-	uint32_t pdn1_set;
-	uint32_t pdn0_clr;
-	uint32_t pdn1_clr;
-	uint32_t pdn0_sta;
-	uint32_t pdn1_sta;
-	uint32_t pdn_md1_set;
-	uint32_t pdn_md2_set;
-	uint32_t pdn_md1_clr;
-	uint32_t pdn_md2_clr;
-	uint32_t pdn_md1_sta;
-	uint32_t pdn_md2_sta;
-	uint32_t pdn_md_mask;
-} __packed;
-
-static struct mtk_uart *const uart_ptr = (void *)UART0_BASE;
-
-static void mtk_uart_tx_flush(void);
-static int mtk_uart_tst_byte(void);
-
-static void mtk_uart_init(void)
-{
-	/* Use a hardcoded divisor for now. */
-	const unsigned int uartclk = 26 * MHz;
-	const unsigned int baudrate = get_uart_baudrate();
-	const uint8_t line_config = UART8250_LCR_WLS_8;  /* 8n1 */
-	unsigned int highspeed, quot, divisor, remainder;
-
-	if (baudrate <= 115200) {
-		highspeed = 0;
-		quot = 16;
-	} else {
-		highspeed = 2;
-		quot = 4;
-	}
-
-	/* Set divisor DLL and DLH  */
-	divisor = uartclk / (quot * baudrate);
-	remainder = uartclk % (quot * baudrate);
-
-	if (remainder >= (quot / 2) * baudrate)
-		divisor += 1;
-
-	mtk_uart_tx_flush();
-
-	/* Disable interrupts. */
-	write8(&uart_ptr->ier, 0);
-	/* Force DTR and RTS to high. */
-	write8(&uart_ptr->mcr, UART8250_MCR_DTR | UART8250_MCR_RTS);
-	/* Set High speed UART register. */
-	write8(&uart_ptr->highspeed, highspeed);
-	/* Set line configuration, access divisor latches. */
-	write8(&uart_ptr->lcr, UART8250_LCR_DLAB | line_config);
-	/* Set the divisor. */
-	write8(&uart_ptr->dll, divisor & 0xff);
-	write8(&uart_ptr->dlm, (divisor >> 8) & 0xff);
-	/* Hide the divisor latches. */
-	write8(&uart_ptr->lcr, line_config);
-	/* Enable FIFOs, and clear receive and transmit. */
-	write8(&uart_ptr->fcr,
-	       UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR |
-	       UART8250_FCR_CLEAR_XMIT);
-
-}
-
-static void mtk_uart_tx_byte(unsigned char data)
-{
-	while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE))
-		;
-	write8(&uart_ptr->thr, data);
-}
-
-static void mtk_uart_tx_flush(void)
-{
-	while (!(read8(&uart_ptr->lsr) & UART8250_LSR_TEMT))
-		;
-}
-
-static unsigned char mtk_uart_rx_byte(void)
-{
-	if (!mtk_uart_tst_byte())
-		return 0;
-	return read8(&uart_ptr->rbr);
-}
-
-static int mtk_uart_tst_byte(void)
-{
-	return (read8(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR;
-}
-
-void uart_init(int idx)
-{
-	mtk_uart_init();
-}
-
-unsigned char uart_rx_byte(int idx)
-{
-	return mtk_uart_rx_byte();
-}
-
-void uart_tx_byte(int idx, unsigned char data)
-{
-	mtk_uart_tx_byte(data);
-}
-
-void uart_tx_flush(int idx)
-{
-	mtk_uart_tx_flush();
-}
-
-#ifndef __PRE_RAM__
-void uart_fill_lb(void *data)
-{
-	struct lb_serial serial;
-	serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
-	serial.baseaddr = UART0_BASE;
-	serial.baud = get_uart_baudrate();
-	serial.regwidth = 4;
-	lb_add_serial(&serial, data);
-
-	lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
-}
-#endif