diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-12-02 22:03:27 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-04 14:11:17 +0000 |
| commit | 55009af42c39f413c49503670ce9bc2858974962 (patch) | |
| tree | 099e9728bfe8066999de4d7a30021eb10bd71d12 /src/soc/mediatek/mt8183/auxadc.c | |
| parent | 1c371572188a90ea16275460dd4ab6bf9966350b (diff) | |
| download | coreboot-55009af42c39f413c49503670ce9bc2858974962.tar.xz | |
Change all clrsetbits_leXX() to clrsetbitsXX()
This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.
This patch was created by running
sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'
across the codebase and cleaning up formatting a bit.
Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/auxadc.c')
| -rw-r--r-- | src/soc/mediatek/mt8183/auxadc.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/mediatek/mt8183/auxadc.c b/src/soc/mediatek/mt8183/auxadc.c index 5460486709..23ce5570bf 100644 --- a/src/soc/mediatek/mt8183/auxadc.c +++ b/src/soc/mediatek/mt8183/auxadc.c @@ -51,19 +51,19 @@ static void mt_auxadc_update_cali(void) } static uint32_t auxadc_get_rawdata(int channel) { - setbits_le32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 10); + setbits32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 10); assert(wait_ms(300, !(read32(&mtk_auxadc->con2) & 0x1))); - clrbits_le32(&mtk_auxadc->con1, 1 << channel); + clrbits32(&mtk_auxadc->con1, 1 << channel); assert(wait_ms(300, !(read32(&mtk_auxadc->data[channel]) & (1 << 12)))); - setbits_le32(&mtk_auxadc->con1, 1 << channel); + setbits32(&mtk_auxadc->con1, 1 << channel); udelay(25); assert(wait_ms(300, read32(&mtk_auxadc->data[channel]) & (1 << 12))); uint32_t value = read32(&mtk_auxadc->data[channel]) & 0x0FFF; - setbits_le32(&mt8183_infracfg->module_sw_cg_1_set, 1 << 10); + setbits32(&mt8183_infracfg->module_sw_cg_1_set, 1 << 10); return value; } |