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author | V Sowmya <v.sowmya@intel.com> | 2020-07-24 09:16:53 +0530 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2020-08-17 05:14:41 +0000 |
commit | 8fd5823c502c2bafdfa70bc0eb1bd8023ee0b692 (patch) | |
tree | 5af1f8fcd95f901ba7360070e3aef2a835f1af52 /src/soc/mediatek/mt8183/dramc_init_setting.c | |
parent | 6d92ab8932ee098516af3e0d208fad536f5c1c55 (diff) | |
download | coreboot-8fd5823c502c2bafdfa70bc0eb1bd8023ee0b692.tar.xz |
mb/intel/jslrvp: Update SLP_Sx assertion widths and PwrCycDur
This patch updates the SLP_Sx assertion widths and power cycle duration
for the Japerlake RVP.
Power cycle duration:
With default value,
S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0
With value set to 1,
S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0
BUG=b:159104150
TEST=Verified that the power cycle duration is ~1.2s with global
reset on JSLRVP.
Change-Id: Ie2a8d959d7ebbf9c24f8c4e8d5c68b70e0ac5708
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/mediatek/mt8183/dramc_init_setting.c')
0 files changed, 0 insertions, 0 deletions