diff options
| author | Hung-Te Lin <hungte@chromium.org> | 2019-09-19 17:49:34 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-17 15:03:33 +0000 |
| commit | 5b29f17ef065fe3492ce3573dbefd037bd645c5b (patch) | |
| tree | fde641c5d4c7414aacd454d1c7984a7b3a426ddd /src/soc/mediatek/mt8183/dramc_pi_basic_api.c | |
| parent | 31ec0c4fdccc856b8f1ab541c21d900b8347810a (diff) | |
| download | coreboot-5b29f17ef065fe3492ce3573dbefd037bd645c5b.tar.xz | |
soc/mediatek/mt8183: Refactor DRAM init by bit fields API
Replace the magic clrsetbits_le32, read32, write32 by SET_BITFIELDS and
other bit field helpers.
Change-Id: I327297dd10718fbef7275fe95c95d00d3ab6ac84
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35471
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/dramc_pi_basic_api.c')
| -rw-r--r-- | src/soc/mediatek/mt8183/dramc_pi_basic_api.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index 46ac22dffe..8f9af608fb 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -212,11 +212,10 @@ void dramc_sw_impedance_save_reg(u8 freq_group) clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 22, sw_impedance[ca_term][1] << 22); - clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[3], - SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE_MASK, - 1 << SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE_SHIFT); - clrbits_le32(&ch[0].phy.shu[0].ca_cmd[0], - SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE_MASK); + SET32_BITFIELDS(&ch[0].phy.shu[0].ca_cmd[3], + SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE, 1); + SET32_BITFIELDS(&ch[0].phy.shu[0].ca_cmd[0], + SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE, 0); clrsetbits_le32(&ch[0].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16); } |