diff options
| author | Huayang Duan <huayang.duan@mediatek.com> | 2018-09-26 21:09:54 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-03 22:22:48 +0000 |
| commit | 7b78a805da0207449c5ea1baf56030ab9f54e2d6 (patch) | |
| tree | 0de9d9fb71948454225b811aac5151c41d3c1905 /src/soc/mediatek/mt8183/dramc_pi_calibration_api.c | |
| parent | 6202d1b51a45e9ed00f742318363920776e32d52 (diff) | |
| download | coreboot-7b78a805da0207449c5ea1baf56030ab9f54e2d6.tar.xz | |
mediatek/mt8183: Add DDR driver of runtime config part
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
patches.
Change-Id: Id1e8862ff6feb9628d37fe5300780ff56865a563
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/28844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/dramc_pi_calibration_api.c')
| -rw-r--r-- | src/soc/mediatek/mt8183/dramc_pi_calibration_api.c | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 1db0514778..7c39b634ef 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -190,22 +190,24 @@ static void dramc_write_dbi_onoff(bool on) (on ? 1 : 0) << SHU1_WODT_DBIWR_SHIFT); } -static void dramc_phy_dcm_disable(u8 chn) +static void dramc_phy_dcm_2_channel(u8 chn, bool en) { - clrsetbits_le32(&ch[chn].phy.misc_cg_ctrl0, - (0x1 << 20) | (0x1 << 19) | 0x3ff << 8, - (0x0 << 20) | (0x1 << 19) | 0x3ff << 8); + clrsetbits_le32(&ch[chn].phy.misc_cg_ctrl0, (0x3 << 19) | (0x3ff << 8), + ((en ? 0 : 0x1) << 19) | ((en ? 0 : 0x1ff) << 9) | (1 << 8)); for (size_t i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) { struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[i]; - setbits_le32(&shu->b[0].dq[8], 0x1fff << 19); - setbits_le32(&shu->b[1].dq[8], 0x1fff << 19); + for (size_t b = 0; b < 2; b++) + clrsetbits_le32(&shu->b[b].dq[8], 0x1fff << 19, + ((en ? 0 : 0x7ff) << 22) | (0x1 << 21) | + ((en ? 0 : 0x3) << 19)); clrbits_le32(&shu->ca_cmd[8], 0x1fff << 19); } - clrbits_le32(&ch[chn].phy.misc_cg_ctrl5, (0x7 << 16) | (0x7 << 20)); + clrsetbits_le32(&ch[chn].phy.misc_cg_ctrl5, (0x7 << 16) | (0x7 << 20), + ((en ? 0x7 : 0) << 16) | ((en ? 0x7 : 0) << 20)); } -static void dramc_enable_phy_dcm(bool en) +void dramc_enable_phy_dcm(bool en) { u32 broadcast_bak = dramc_get_broadcast(); dramc_set_broadcast(DRAMC_BROADCAST_OFF); @@ -250,8 +252,7 @@ static void dramc_enable_phy_dcm(bool en) clrsetbits_le32(&shu->ca_cmd[7], mask, value); } - if (!en) - dramc_phy_dcm_disable(chn); + dramc_phy_dcm_2_channel(chn, en); } dramc_set_broadcast(broadcast_bak); } @@ -270,7 +271,7 @@ static void reset_delay_chain_before_calibration(void) } } -static void dramc_hw_gating_onoff(u8 chn, bool on) +void dramc_hw_gating_onoff(u8 chn, bool on) { clrsetbits_le32(&ch[chn].ao.shuctrl2, 0x3 << 14, (on ? 0x3 : 0) << 14); |