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| author | Huayang Duan <huayang.duan@mediatek.com> | 2020-04-20 19:33:28 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-20 09:50:45 +0000 |
| commit | 062646670fe0b750e1c8398321c21054e30ff054 (patch) | |
| tree | a347a7d8a8e648ad0bd0ab8258020311f93b2c7b /src/soc/mediatek/mt8183/dramc_pi_calibration_api.c | |
| parent | efaf1b32ba1eb69b8968de7e0f67e8fc66fca0d5 (diff) | |
| download | coreboot-062646670fe0b750e1c8398321c21054e30ff054.tar.xz | |
soc/mediatek/mt8183: Set CA and DQ vref range to correct value
The CA vref should alway select range[1]. But in fast calibration flow,
we missed the range selection and caused the CA vref to use the range[0] value.
The DQ vref should select correct range that corresponds to current frequency,
that is for 1600Mbps, 2400Mbps to select range[1], for 3200Mbps and 3600Mbps
to select range[0].
Refer to the 'JESD209-4 - Low Power Double Data Rate 4X(LPDDR4X).pdf',
used MR12 to set Vref(CA) levels, used MR14 to set VREF(DQ) levels.
MR12 range[0] values from 15.0% to 44.9%, range[1] values from 32.9% to 62.9%,
MR14 range[0] and range[1] values same as MR12.
BUG=b:153614919
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: Ie7680b1bf0c29c946d18e3b27626ce6f31c4216b
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40525
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/dramc_pi_calibration_api.c')
| -rw-r--r-- | src/soc/mediatek/mt8183/dramc_pi_calibration_api.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 7242dd3ce8..aac6d17ed6 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -220,9 +220,7 @@ static void dramc_write_leveling(u8 chn, u8 rank, u8 freq_group, { dramc_auto_refresh_switch(chn, false); - if (rank == RANK_0 && (freq_group == LP4X_DDR3600 || - freq_group == LP4X_DDR1600 || - freq_group == LP4X_DDR2400)) + if (rank == RANK_0) write_leveling_move_dqs_instead_of_clk(chn); SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], @@ -265,8 +263,11 @@ static void dramc_cmd_bus_training(u8 chn, u8 rank, u8 freq_group, SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], SHU1_R0_CA_CMD9_RG_RK0_ARPI_CS, cs_dly); + final_vref |= (1 << 6); + /* CBT set vref */ dramc_mode_reg_write_by_rank(chn, rank, 12, final_vref); + dramc_dbg("final_vref: %#x\n", final_vref); } static void dramc_read_dbi_onoff(size_t chn, bool on) @@ -1822,7 +1823,7 @@ static u8 dramc_window_perbit_cal(u8 chn, u8 rank, u8 freq_group, vref_end = vref_begin + 1; dramc_dbg("bypass RX vref: %d\n", vref_begin); } else if (type == TX_WIN_DQ_ONLY) { - vref_begin = params->tx_vref[chn][rank]; + vref_begin = params->tx_vref[chn][rank] | (vref_range << 6); vref_end = vref_begin + 1; dramc_dbg("bypass TX vref: %d\n", vref_begin); } |