diff options
author | Huayang Duan <huayang.duan@mediatek.com> | 2020-06-08 19:19:34 +0800 |
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committer | Hung-Te Lin <hungte@chromium.org> | 2020-08-06 03:02:40 +0000 |
commit | 92fb91935b7e8736dd4e74a446215bd823b9615f (patch) | |
tree | 005d1712f161010da2d675cabcfadc4ad2d6cbb5 /src/soc/mediatek/mt8183/dramc_pi_calibration_api.c | |
parent | cac990f18668a979397d706361d2690fe1d7a220 (diff) | |
download | coreboot-92fb91935b7e8736dd4e74a446215bd823b9615f.tar.xz |
soc/mediatek/mt8183: Adjust tRFCab and tRFCpb by the density value
Different density should correspond to different tRFCab and tRFCpb
timing.
BUG=none
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: I2599fcd620cdefe2e12480932ffd75e0416b9545
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8183/dramc_pi_calibration_api.c')
-rw-r--r-- | src/soc/mediatek/mt8183/dramc_pi_calibration_api.c | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index ee9b9b6b70..50d847f542 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -130,6 +130,19 @@ void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value) dramc_dbg("Write MR%d =0x%x\n", mr_idx, value); } +static u8 dramc_mode_reg_read_by_rank(u8 chn, u8 rank, u8 mr_idx) +{ + u8 value; + u32 rk_bak = READ32_BITFIELD(&ch[chn].ao.mrs, MRS_MRRRK); + + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRRRK, rank); + value = dramc_mode_reg_read(chn, mr_idx); + SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRRRK, rk_bak); + + dramc_dbg("Mode reg read rank%d MR%d = %#x\n", rank, mr_idx, value); + return value; +} + static void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, u8 mr_idx, u8 value) { @@ -2694,6 +2707,55 @@ void dramc_dqs_precalculation_preset(void) } } +void get_dram_info_after_cal(u8 *density_result) +{ + u8 vendor_id, density, max_density = 0; + u32 ddr_size, max_size = 0; + + vendor_id = dramc_mode_reg_read_by_rank(CHANNEL_A, RANK_0, 5); + dramc_show("Vendor id is %#x\n", vendor_id); + + for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { + density = dramc_mode_reg_read_by_rank(CHANNEL_A, rk, 8); + dramc_dbg("MR8 %#x\n", density); + density = (density >> 2) & 0xf; + + switch (density) { + case 0x0: + ddr_size = 4; + break; + case 0x1: + ddr_size = 6; + break; + case 0x2: + ddr_size = 8; + break; + case 0x3: + ddr_size = 12; + break; + case 0x4: + ddr_size = 16; + break; + case 0x5: + ddr_size = 24; + break; + case 0x6: + ddr_size = 32; + break; + default: + ddr_size = 0; + break; + } + if (ddr_size > max_size) { + max_size = ddr_size; + max_density = density; + } + dramc_dbg("RK%d size %dGb, density:%d\n", rk, ddr_size, max_density); + } + + *density_result = max_density; +} + int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group, const struct mr_value *mr) { |