diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-12-02 22:03:27 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-04 14:11:17 +0000 |
| commit | 55009af42c39f413c49503670ce9bc2858974962 (patch) | |
| tree | 099e9728bfe8066999de4d7a30021eb10bd71d12 /src/soc/mediatek/mt8183/dsi.c | |
| parent | 1c371572188a90ea16275460dd4ab6bf9966350b (diff) | |
| download | coreboot-55009af42c39f413c49503670ce9bc2858974962.tar.xz | |
Change all clrsetbits_leXX() to clrsetbitsXX()
This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.
This patch was created by running
sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'
across the codebase and cleaning up formatting a bit.
Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/dsi.c')
| -rw-r--r-- | src/soc/mediatek/mt8183/dsi.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c index 604592f5cb..7f5ac0a747 100644 --- a/src/soc/mediatek/mt8183/dsi.c +++ b/src/soc/mediatek/mt8183/dsi.c @@ -49,19 +49,19 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) txdiv1 = 0; } - clrbits_le32(&mipi_tx->pll_con4, BIT(11) | BIT(10)); - setbits_le32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON); + clrbits32(&mipi_tx->pll_con4, BIT(11) | BIT(10)); + setbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON); udelay(30); - clrbits_le32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN); + clrbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN); pcw = (u64)data_rate * (1 << txdiv0) * (1 << txdiv1); pcw <<= 24; pcw /= CLK26M_HZ / MHz; write32(&mipi_tx->pll_con0, pcw); - clrsetbits_le32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8); + clrsetbits32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8); udelay(30); - setbits_le32(&mipi_tx->pll_con1, RG_DSI_PLL_EN); + setbits32(&mipi_tx->pll_con1, RG_DSI_PLL_EN); /* BG_LPF_EN / BG_CORE_EN */ write32(&mipi_tx->lane_con, 0x3fff0180); @@ -69,13 +69,13 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes) write32(&mipi_tx->lane_con, 0x3fff00c0); /* Switch OFF each Lane */ - clrbits_le32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN); - clrbits_le32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN); - clrbits_le32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN); - clrbits_le32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN); - clrbits_le32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN); + clrbits32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN); - setbits_le32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN); + setbits32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN); } void mtk_dsi_reset(void) |