diff options
| author | Huayang Duan <huayang.duan@mediatek.com> | 2019-12-30 13:19:05 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-06 08:00:48 +0000 |
| commit | 25930f4a3f7c518afadeb1d0298f9750707748e8 (patch) | |
| tree | c14be78017e72b65f56b1348668caeca1a18b982 /src/soc/mediatek/mt8183/emi.c | |
| parent | 998737df71c3c2ed97da36305ef065eb280cf2b2 (diff) | |
| download | coreboot-25930f4a3f7c518afadeb1d0298f9750707748e8.tar.xz | |
soc/mediatek/mt8183: Do TX tracking for DRAM DVFS feature
The TX window will offset to edge during DVFS switch, which may cause
TX data transmission error and random kernel crash. Therefore, use the
standard dqsosc (DQS Oscillator) for TX window tracking.
BUG=b:142358843
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: Idcf9213a488e795df3faf64b03588cfe55cb2f81
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/emi.c')
| -rw-r--r-- | src/soc/mediatek/mt8183/emi.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index e7cbda15d9..f1a2e39563 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -34,7 +34,7 @@ static const u8 freq_shuffle_emcp[DRAM_DFS_SHUFFLE_MAX] = { [DRAM_DFS_SHUFFLE_3] = LP4X_DDR1600, }; -u32 frequency_table[LP4X_DDRFREQ_MAX] = { +static const u32 frequency_table[LP4X_DDRFREQ_MAX] = { [LP4X_DDR1600] = 1600, [LP4X_DDR2400] = 2400, [LP4X_DDR3200] = 3200, @@ -77,6 +77,13 @@ u32 dramc_get_broadcast(void) return read32(&mt8183_infracfg->dramc_wbr); } +u32 get_shu_freq(u8 shu) +{ + const u8 *freq_tbl = CONFIG(MT8183_DRAM_EMCP) ? + freq_shuffle_emcp : freq_shuffle; + return frequency_table[freq_tbl[shu]]; +} + static u64 get_ch_rank_size(u8 chn, u8 rank) { u32 shift_for_16bit = 1; |