diff options
author | Po Xu <jg_poxu@mediatek.com> | 2018-07-16 18:41:49 +0800 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-20 13:51:02 +0000 |
commit | f71f1796ce075e0b0a7821aadce9de0a59af2528 (patch) | |
tree | c06acc8b9c454b85b490be5832aad9eecce79d87 /src/soc/mediatek/mt8183/gpio.c | |
parent | 71d227b1085b5f54b11a6fcfa9419597ee5c9f56 (diff) | |
download | coreboot-f71f1796ce075e0b0a7821aadce9de0a59af2528.tar.xz |
mediatek/mt8183: Add GPIO support
This patch implements gpio_set_pull() and links the common MediaTek
GPIO code to support IO config for other drivers (ex. SPI) and the
requested functions in src/include/gpio.h.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: Ia2b0d88e9b70c9ad148797d77dc9e79ce1bcb64a
Signed-off-by: Po Xu <jg_poxu@mediatek.com>
Reviewed-on: https://review.coreboot.org/27417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/gpio.c')
-rw-r--r-- | src/soc/mediatek/mt8183/gpio.c | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8183/gpio.c b/src/soc/mediatek/mt8183/gpio.c new file mode 100644 index 0000000000..d555c3356b --- /dev/null +++ b/src/soc/mediatek/mt8183/gpio.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <gpio.h> + +enum { + EN_OFFSET = 0x60, + SEL_OFFSET = 0x80, +}; + +static void gpio_set_pull_pupd(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + void *reg = GPIO_TO_IOCFG_BASE(gpio.base) + gpio.offset; + int bit = gpio.bit; + + if (enable == GPIO_PULL_ENABLE) { + if (select == GPIO_PULL_DOWN) + setbits_le32(reg, 1 << (bit + 2)); + else + clrbits_le32(reg, 1 << (bit + 2)); + } + + if (enable == GPIO_PULL_ENABLE) + clrsetbits_le32(reg, 3 << bit, 1 << bit); + else + clrbits_le32(reg, 3 << bit); +} + +static void gpio_set_pull_en_sel(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + void *reg = GPIO_TO_IOCFG_BASE(gpio.base) + gpio.offset; + int bit = gpio.bit; + + if (enable == GPIO_PULL_ENABLE) { + if (select == GPIO_PULL_DOWN) + clrbits_le32(reg + SEL_OFFSET, 1 << bit); + else + setbits_le32(reg + SEL_OFFSET, 1 << bit); + } + + if (enable == GPIO_PULL_ENABLE) + setbits_le32(reg + EN_OFFSET, 1 << bit); + else + clrbits_le32(reg + EN_OFFSET, 1 << bit); +} + +void gpio_set_pull(gpio_t gpio, enum pull_enable enable, + enum pull_select select) +{ + if (gpio.flag) + gpio_set_pull_pupd(gpio, enable, select); + else + gpio_set_pull_en_sel(gpio, enable, select); +} |