soc/mediatek/mt8183: Add DSI driver

The MT8183 display serial interface (DSI) is based on MIPI
Alliance Specification, supporting high-speed serial data
transfer between host processor and peripheral devices such
as display modules.

DSI supports both video mode and command mode data transfer
defined in MIPI spec, and it also provides bidirectional
transmission with low-power mode to receive messages from
the peripheral.

Reference: MT8183 Application Processor Functional Spec,
 6.7 Display Serial Interface (DSI)

BUG=b:80501386,b:117254947
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: Ic413f524ca0b36f0b01f723a71fe9745e2710cd2
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

2 files changed, 70 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h
index bb44f9bb45..c267a1473e 100644
--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h
@@ -51,6 +51,7 @@ enum {
 	IOCFG_RT_BASE		= IO_PHYS + 0x01C50000,
 	IOCFG_RM_BASE		= IO_PHYS + 0x01D20000,
 	IOCFG_RB_BASE		= IO_PHYS + 0x01D30000,
+	MIPITX_BASE             = IO_PHYS + 0x01E50000,
 	IOCFG_LB_BASE		= IO_PHYS + 0x01E70000,
 	IOCFG_LM_BASE		= IO_PHYS + 0x01E80000,
 	IOCFG_BL_BASE		= IO_PHYS + 0x01E90000,
@@ -69,6 +70,7 @@ enum {
 	DISP_AAL0_BASE		= IO_PHYS + 0x04010000,
 	DISP_GAMMA0_BASE	= IO_PHYS + 0x04011000,
 	DISP_DITHER0_BASE	= IO_PHYS + 0x04012000,
+	DSI0_BASE               = IO_PHYS + 0x04014000,
 	DISP_MUTEX_BASE		= IO_PHYS + 0x04016000,
 	SMI_LARB0		= IO_PHYS + 0x04017000,
 	SMI_BASE		= IO_PHYS + 0x04019000,
diff --git a/src/soc/mediatek/mt8183/include/soc/dsi.h b/src/soc/mediatek/mt8183/include/soc/dsi.h
new file mode 100644
index 0000000000..8813f94982
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/dsi.h
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_MEDIATEK_MT8183_DSI_H
+#define SOC_MEDIATEK_MT8183_DSI_H
+
+#include <soc/dsi_common.h>
+
+/* DSI features */
+#define MTK_DSI_MIPI_RATIO_NUMERATOR 100
+#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100
+#define MTK_DSI_DATA_RATE_MIN_MHZ 125
+#define MTK_DSI_HAVE_SIZE_CON 1
+#define PIXEL_STREAM_CUSTOM_HEADER 0xb
+
+/* MIPITX is SOC specific and cannot live in common. */
+
+/* MIPITX_REG */
+struct mipi_tx_regs {
+	u32 reserved0[3];
+	u32 lane_con;
+	u32 reserved1[6];
+	u32 pll_pwr;
+	u32 pll_con0;
+	u32 pll_con1;
+	u32 pll_con2;
+	u32 pll_con3;
+	u32 pll_con4;
+	u32 reserved2[65];
+	u32 d2_sw_ctl_en;
+	u32 reserved3[63];
+	u32 d0_sw_ctl_en;
+	u32 reserved4[56];
+	u32 ck_ckmode_en;
+	u32 reserved5[6];
+	u32 ck_sw_ctl_en;
+	u32 reserved6[63];
+	u32 d1_sw_ctl_en;
+	u32 reserved7[63];
+	u32 d3_sw_ctl_en;
+};
+
+check_member(mipi_tx_regs, pll_con4, 0x3c);
+check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
+static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE;
+
+/* Register values */
+#define DSI_CK_CKMODE_EN	BIT(0)
+#define DSI_SW_CTL_EN		BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON	BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN	BIT(1)
+
+#define RG_DSI_PLL_EN		BIT(4)
+#define RG_DSI_PLL_POSDIV	(0x7 << 8)
+
+#endif