summaryrefslogtreecommitdiff
path: root/src/soc/mediatek/mt8183/include
diff options
context:
space:
mode:
authorChuanjia Liu <Chuanjia.Liu@mediatek.com>2018-11-26 14:20:09 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-12-05 13:34:57 +0000
commit3a065f1a76feb4f23af6708caef5f912292610fd (patch)
tree5b159ceadd0fdf6aaa1b60b139c0fda7e5a0b5c8 /src/soc/mediatek/mt8183/include
parentd5d20d03fea5d50152fac783cb0985dbaa66d782 (diff)
downloadcoreboot-3a065f1a76feb4f23af6708caef5f912292610fd.tar.xz
mediatek: Share GPIO external interrupts (EINT) code among similar SoCs
Refactor GPIO EINT code which can be reused among similar SoCs. BUG=b:80501386 BRANCH=none TEST=emerge-elm coreboot; emerge-kukui coreboot Change-Id: Ib01b43cf1aa4082d7d968fe1ef82f75e8cf05b8b Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/29837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/include')
-rw-r--r--src/soc/mediatek/mt8183/include/soc/addressmap.h5
-rw-r--r--src/soc/mediatek/mt8183/include/soc/gpio.h15
-rw-r--r--src/soc/mediatek/mt8183/include/soc/gpio_base.h31
3 files changed, 34 insertions, 17 deletions
diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h
index 7578c289e1..d41b2b942e 100644
--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h
@@ -26,8 +26,9 @@ enum {
INFRACFG_AO_BASE = IO_PHYS + 0x00001000,
GPIO_BASE = IO_PHYS + 0x00005000,
SPM_BASE = IO_PHYS + 0x00006000,
- RGU_BASE = IO_PHYS + 0x00007000,
+ RGU_BASE = IO_PHYS + 0x00007000,
GPT_BASE = IO_PHYS + 0x00008000,
+ EINT_BASE = IO_PHYS + 0x0000B000,
APMIXED_BASE = IO_PHYS + 0x0000C000,
PWRAP_BASE = IO_PHYS + 0x0000D000,
EMI_BASE = IO_PHYS + 0x00219000,
@@ -35,7 +36,7 @@ enum {
DRAMC_CH_BASE = IO_PHYS + 0x00228000,
AUXADC_BASE = IO_PHYS + 0x01001000,
UART0_BASE = IO_PHYS + 0x01002000,
- SPI0_BASE = IO_PHYS + 0x0100A000,
+ SPI0_BASE = IO_PHYS + 0x0100A000,
SPI1_BASE = IO_PHYS + 0x01010000,
SPI2_BASE = IO_PHYS + 0x01012000,
SPI3_BASE = IO_PHYS + 0x01013000,
diff --git a/src/soc/mediatek/mt8183/include/soc/gpio.h b/src/soc/mediatek/mt8183/include/soc/gpio.h
index 1faab44720..c3c8dda26d 100644
--- a/src/soc/mediatek/mt8183/include/soc/gpio.h
+++ b/src/soc/mediatek/mt8183/include/soc/gpio.h
@@ -26,17 +26,6 @@ enum {
GPIO_MODE_BITS = 4,
};
-typedef union {
- u32 raw;
- struct {
- u32 id : 8;
- u32 flag : 3;
- u32 bit : 5;
- u32 base : 8;
- u32 offset : 8;
- };
-} gpio_t;
-
#define IOCFG_TO_GPIO_BASE(x) ((x >> 16) & 0xff)
#define GPIO_TO_IOCFG_BASE(x) ((void *)(IOCFG_RT_BASE & 0xff000000) + \
((x) << 16))
@@ -628,8 +617,4 @@ check_member(gpio_regs, mode[22].val, 0x460);
static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE);
-void gpio_set_pull(gpio_t gpio, enum pull_enable enable,
- enum pull_select select);
-void gpio_set_mode(gpio_t gpio, int mode);
-
#endif
diff --git a/src/soc/mediatek/mt8183/include/soc/gpio_base.h b/src/soc/mediatek/mt8183/include/soc/gpio_base.h
new file mode 100644
index 0000000000..60b80bc63f
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/gpio_base.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef SOC_MEDIATEK_MT8183_GPIO_BASE_H
+#define SOC_MEDIATEK_MT8183_GPIO_BASE_H
+
+#include <stdint.h>
+
+typedef union {
+ u32 raw;
+ struct {
+ u32 id : 8;
+ u32 flag : 3;
+ u32 bit : 5;
+ u32 base : 8;
+ u32 offset : 8;
+ };
+} gpio_t;
+
+#endif