diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-12-02 22:03:27 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-04 14:11:17 +0000 |
| commit | 55009af42c39f413c49503670ce9bc2858974962 (patch) | |
| tree | 099e9728bfe8066999de4d7a30021eb10bd71d12 /src/soc/mediatek/mt8183/spm.c | |
| parent | 1c371572188a90ea16275460dd4ab6bf9966350b (diff) | |
| download | coreboot-55009af42c39f413c49503670ce9bc2858974962.tar.xz | |
Change all clrsetbits_leXX() to clrsetbitsXX()
This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.
This patch was created by running
sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'
across the codebase and cleaning up formatting a bit.
Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/spm.c')
| -rw-r--r-- | src/soc/mediatek/mt8183/spm.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c index 9a08782953..024fe1c9fc 100644 --- a/src/soc/mediatek/mt8183/spm.c +++ b/src/soc/mediatek/mt8183/spm.c @@ -77,16 +77,16 @@ static int spm_register_init(void) MD_DDR_EN_1_DBC_LEN | CONN_DDR_EN_DBC_LEN); - clrsetbits_le32(&mtk_spm->spare_ack_mask, - SPARE_ACK_MASK_B_BIT1, - SPARE_ACK_MASK_B_BIT0); + clrsetbits32(&mtk_spm->spare_ack_mask, + SPARE_ACK_MASK_B_BIT1, + SPARE_ACK_MASK_B_BIT0); write32(&mtk_spm->sysrom_con, IFR_SRAMROM_ROM_PDN); write32(&mtk_spm->spm_pc_trace_con, SPM_PC_TRACE_OFFSET | SPM_PC_TRACE_HW_EN_LSB); - setbits_le32(&mtk_spm->spare_src_req_mask, SPARE1_DDREN_MASK_B_LSB); + setbits32(&mtk_spm->spare_src_req_mask, SPARE1_DDREN_MASK_B_LSB); return 0; } @@ -131,9 +131,9 @@ static int spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc) write32(&mtk_spm->pcm_pwr_io_en, 0); - clrsetbits_le32(&mtk_spm->pcm_con1, - PCM_TIMER_EN_LSB, - SPM_REGWR_CFG_KEY); + clrsetbits32(&mtk_spm->pcm_con1, + PCM_TIMER_EN_LSB, + SPM_REGWR_CFG_KEY); write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB | PCM_SW_RESET_LSB); |