diff options
| author | Jiaxin Yu <jiaxin.yu@mediatek.com> | 2019-04-25 17:14:26 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-29 12:19:49 +0000 |
| commit | 5a69491a01b6fe32a975aee557348acc84fc7a40 (patch) | |
| tree | a7a7b60c2a8a3e132cf7ea3a1a3e4ead820f1718 /src/soc/mediatek/mt8183 | |
| parent | da79f5c91d94883589a3530f4cc30231a9826bf0 (diff) | |
| download | coreboot-5a69491a01b6fe32a975aee557348acc84fc7a40.tar.xz | |
mediatek/mt8183: Init audio related clock
Enable audio clock, intbus clock, infra clock and mtkaif
26m clock.Needed by audio playback in firmware.
BUG=b:117254418
BRANCH=none
TEST=Build pass and verified on kukui p1 board
Change-Id: I88060d9796cc23ad7f524943f36869e1ec85073d
Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8183')
| -rw-r--r-- | src/soc/mediatek/mt8183/pll.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 61aa2de7fb..8608b4ac10 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -356,4 +356,16 @@ void mt_pll_init(void) /* enable [14] dramc_pll104m_ck */ setbits_le32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14); + + /* enable audio clock */ + setbits_le32(&mtk_topckgen->clk_cfg_5_clr, 1 << 7); + + /* enable intbus clock */ + setbits_le32(&mtk_topckgen->clk_cfg_5_clr, 1 << 15); + + /* enable infra clock */ + setbits_le32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 25); + + /* enable mtkaif 26m clock */ + setbits_le32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4); } |