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| author | Tristan Shieh <tristan.shieh@mediatek.com> | 2019-07-10 15:02:39 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-11 15:10:03 +0000 |
| commit | e13a65c5ffd066272f1a224120bbc5788f56106c (patch) | |
| tree | 49a06b90cd8748b14da109552ee82ea948324966 /src/soc/mediatek/mt8183 | |
| parent | 447badd1cfbf70a26f3e6fb0b84d8166dc732bc4 (diff) | |
| download | coreboot-e13a65c5ffd066272f1a224120bbc5788f56106c.tar.xz | |
mediatek: Fill in input_hertz to coreboot table
Set input_hertz to 26 MHz.
BUG=b:134351649
BRANCH=none
TEST=emerge-kukui coreboot; emerge-elm coreboot
Change-Id: I7f9c329ae5d610f2516e60f06b2ac96ebbeaa897
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8183')
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/pll.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8183/include/soc/pll.h b/src/soc/mediatek/mt8183/include/soc/pll.h index 3807e0087e..5a24e75692 100644 --- a/src/soc/mediatek/mt8183/include/soc/pll.h +++ b/src/soc/mediatek/mt8183/include/soc/pll.h @@ -268,6 +268,7 @@ enum { /* top_mux rate */ enum { SPI_HZ = MAINPLL_D5_D2_HZ, + UART_HZ = CLK26M_HZ, }; enum { |