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authorYu-Ping Wu <yupingso@google.com>2019-08-16 13:38:32 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-08-21 09:27:39 +0000
commit4b3047833f9bce984e2710b98be5100f684cc337 (patch)
treefc8f38d2196f0233f2274a5147a2072a588a3dfd /src/soc/mediatek/mt8183
parent7fc006f7452ff944184e2091d670a647b96f9aac (diff)
downloadcoreboot-4b3047833f9bce984e2710b98be5100f684cc337.tar.xz
mediatek: Use GPIO based SPI CS
Some boards (e.g., Kukui) need GPIO based CS for SPI0. This patch changes the pinmux and binds the pins to the correponding SPIs. When using GPIO based SPI CS, we need to manually make CS log/high before/after SPI transactions. BUG=b:132311067 BRANCH=none TEST=Verified that b/132311067 is irreproducible Change-Id: I61653fb19242b6ee6be9a45545a8b66e5c9c7cad Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8183')
-rw-r--r--src/soc/mediatek/mt8183/spi.c21
1 files changed, 14 insertions, 7 deletions
diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c
index 982f6439ed..7672db7993 100644
--- a/src/soc/mediatek/mt8183/spi.c
+++ b/src/soc/mediatek/mt8183/spi.c
@@ -24,21 +24,27 @@
struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = {
{
.regs = (void *)SPI0_BASE,
+ .cs_gpio = GPIO(SPI_CSB),
},
{
.regs = (void *)SPI1_BASE,
+ .cs_gpio = GPIO(SPI1_CSB),
},
{
.regs = (void *)SPI2_BASE,
+ .cs_gpio = GPIO(EINT0),
},
{
.regs = (void *)SPI3_BASE,
+ .cs_gpio = GPIO(DPI_D9),
},
{
.regs = (void *)SPI4_BASE,
+ .cs_gpio = GPIO(DPI_D5),
},
{
.regs = (void *)SPI5_BASE,
+ .cs_gpio = GPIO(DPI_D1),
}
};
@@ -48,41 +54,42 @@ struct pad_func {
};
#define PAD_FUNC(name, func) {PAD_##name##_ID, PAD_##name##_FUNC_##func}
+#define PAD_FUNC_GPIO(name) {PAD_##name##_ID, 0}
static const struct pad_func pad0_funcs[SPI_BUS_NUMBER][4] = {
{
PAD_FUNC(SPI_MI, SPI0_MI),
- PAD_FUNC(SPI_CSB, SPI0_CSB),
+ PAD_FUNC_GPIO(SPI_CSB),
PAD_FUNC(SPI_MO, SPI0_MO),
PAD_FUNC(SPI_CLK, SPI0_CLK),
},
{
PAD_FUNC(SPI1_MI, SPI1_A_MI),
- PAD_FUNC(SPI1_CSB, SPI1_A_CSB),
+ PAD_FUNC_GPIO(SPI1_CSB),
PAD_FUNC(SPI1_MO, SPI1_A_MO),
PAD_FUNC(SPI1_CLK, SPI1_A_CLK),
},
{
PAD_FUNC(KPCOL1, SPI2_MI),
- PAD_FUNC(EINT0, SPI2_CSB),
+ PAD_FUNC_GPIO(EINT0),
PAD_FUNC(EINT1, SPI2_MO),
PAD_FUNC(EINT2, SPI2_CLK),
},
{
PAD_FUNC(DPI_D8, SPI3_MI),
- PAD_FUNC(DPI_D9, SPI3_CSB),
+ PAD_FUNC_GPIO(DPI_D9),
PAD_FUNC(DPI_D10, SPI3_MO),
PAD_FUNC(DPI_D11, SPI3_CLK),
},
{
PAD_FUNC(DPI_D4, SPI4_MI),
- PAD_FUNC(DPI_D5, SPI4_CSB),
+ PAD_FUNC_GPIO(DPI_D5),
PAD_FUNC(DPI_D6, SPI4_MO),
PAD_FUNC(DPI_D7, SPI4_CLK),
},
{
PAD_FUNC(DPI_D0, SPI5_MI),
- PAD_FUNC(DPI_D1, SPI5_CSB),
+ PAD_FUNC_GPIO(DPI_D1),
PAD_FUNC(DPI_D2, SPI5_MO),
PAD_FUNC(DPI_D3, SPI5_CLK),
}
@@ -90,7 +97,7 @@ static const struct pad_func pad0_funcs[SPI_BUS_NUMBER][4] = {
static const struct pad_func bus1_pad1_funcs[4] = {
PAD_FUNC(EINT7, SPI1_B_MI),
- PAD_FUNC(EINT8, SPI1_B_CSB),
+ PAD_FUNC_GPIO(EINT8),
PAD_FUNC(EINT9, SPI1_B_MO),
PAD_FUNC(EINT10, SPI1_B_CLK),
};