Change all clrsetbits_leXX() to clrsetbitsXX()

This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.

This patch was created by running

 sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'

across the codebase and cleaning up formatting a bit.

Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

13 files changed, 807 insertions, 807 deletions

diff --git a/src/soc/mediatek/mt8183/auxadc.c b/src/soc/mediatek/mt8183/auxadc.c
index 5460486709..23ce5570bf 100644
--- a/src/soc/mediatek/mt8183/auxadc.c
+++ b/src/soc/mediatek/mt8183/auxadc.c
@@ -51,19 +51,19 @@ static void mt_auxadc_update_cali(void)
 }
 static uint32_t auxadc_get_rawdata(int channel)
 {
-	setbits_le32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 10);
+	setbits32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 10);
 	assert(wait_ms(300, !(read32(&mtk_auxadc->con2) & 0x1)));
 
-	clrbits_le32(&mtk_auxadc->con1, 1 << channel);
+	clrbits32(&mtk_auxadc->con1, 1 << channel);
 	assert(wait_ms(300, !(read32(&mtk_auxadc->data[channel]) & (1 << 12))));
 
-	setbits_le32(&mtk_auxadc->con1, 1 << channel);
+	setbits32(&mtk_auxadc->con1, 1 << channel);
 	udelay(25);
 	assert(wait_ms(300, read32(&mtk_auxadc->data[channel]) & (1 << 12)));
 
 	uint32_t value = read32(&mtk_auxadc->data[channel]) & 0x0FFF;
 
-	setbits_le32(&mt8183_infracfg->module_sw_cg_1_set, 1 << 10);
+	setbits32(&mt8183_infracfg->module_sw_cg_1_set, 1 << 10);
 
 	return value;
 }
diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c
index 3c2b0fd662..50d6caf776 100644
--- a/src/soc/mediatek/mt8183/ddp.c
+++ b/src/soc/mediatek/mt8183/ddp.c
@@ -42,7 +42,7 @@ static void disp_config_main_path_mutex(void)
 
 static void ovl_bgclr_in_sel(u32 idx)
 {
-	setbits_le32(&disp_ovl[idx]->datapath_con, BIT(2));
+	setbits32(&disp_ovl[idx]->datapath_con, BIT(2));
 }
 
 static void enable_pq(struct disp_pq_regs *const regs, u32 width, u32 height,
@@ -74,10 +74,10 @@ static void main_disp_path_setup(u32 width, u32 height, u32 vrefresh)
 
 static void disp_clock_on(void)
 {
-	clrbits_le32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL);
+	clrbits32(&mmsys_cfg->mmsys_cg_con0, CG_CON0_DISP_ALL);
 
-	clrbits_le32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_DSI0 |
-						CG_CON1_DISP_DSI0_INTERFACE);
+	clrbits32(&mmsys_cfg->mmsys_cg_con1, CG_CON1_DISP_DSI0 |
+					     CG_CON1_DISP_DSI0_INTERFACE);
 }
 
 void mtk_ddp_init(void)
diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c
index 2a36b48d5d..74fa0e2f1d 100644
--- a/src/soc/mediatek/mt8183/dramc_init_setting.c
+++ b/src/soc/mediatek/mt8183/dramc_init_setting.c
@@ -39,7 +39,7 @@ static void cke_fix_onoff(int option, u8 chn)
 		off = (1 - option);
 	}
 
-	clrsetbits_le32(&ch[chn].ao.ckectrl,
+	clrsetbits32(&ch[chn].ao.ckectrl,
 		(0x1 << 6) | (0x1 << 7), (on << 6) | (off << 7));
 }
 
@@ -67,13 +67,13 @@ static void dvfs_settings(u8 freq_group)
 
 	dll_idle = dll_idle << 1;
 	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		setbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 5);
-		setbits_le32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 29);
-		clrsetbits_le32(&ch[0].ao.shuctrl2, 0x7f, dll_idle);
+		setbits32(&ch[chn].ao.dvfsdll, 0x1 << 5);
+		setbits32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 29);
+		clrsetbits32(&ch[0].ao.shuctrl2, 0x7f, dll_idle);
 
-		setbits_le32(&ch[0].phy.misc_ctrl0, 0x3 << 19);
-		setbits_le32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 24);
-		setbits_le32(&ch[chn].ao.dvfsdll, 0x1 << 7);
+		setbits32(&ch[0].phy.misc_ctrl0, 0x3 << 19);
+		setbits32(&ch[chn].phy.dvfs_emi_clk, 0x1 << 24);
+		setbits32(&ch[chn].ao.dvfsdll, 0x1 << 7);
 	}
 }
 
@@ -120,11 +120,11 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group)
 		ca_dll_mode[CHANNEL_A] = DLL_MASTER;
 	ca_dll_mode[CHANNEL_B] = DLL_SLAVE;
 
-	clrbits_le32(&ch[chn].phy.shu[0].pll[4], 0xffff);
-	clrbits_le32(&ch[chn].phy.shu[0].pll[6], 0xffff);
-	setbits_le32(&ch[chn].phy.misc_shu_opt, (chn + 1) << 18);
-	clrsetbits_le32(&ch[chn].phy.ckmux_sel, 0x3 << 18 | 0x3 << 16, 0x0);
-	clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[0], 0x3 << 18, 0x1 << 18);
+	clrbits32(&ch[chn].phy.shu[0].pll[4], 0xffff);
+	clrbits32(&ch[chn].phy.shu[0].pll[6], 0xffff);
+	setbits32(&ch[chn].phy.misc_shu_opt, (chn + 1) << 18);
+	clrsetbits32(&ch[chn].phy.ckmux_sel, 0x3 << 18 | 0x3 << 16, 0x0);
+	clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[0], 0x3 << 18, 0x1 << 18);
 
 	SET32_BITFIELDS(&ch[chn].ao.dvfsdll, DVFSDLL_R_BYPASS_1ST_DLL_SHU1,
 			ca_dll_mode[chn] == DLL_SLAVE);
@@ -136,7 +136,7 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group)
 	u8 idle_cnt = is_master ? 0x9 : 0x7;
 	u8 fast_psjp = is_master ? 0x1 : 0x0;
 
-	clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[0],
+	clrsetbits32(&ch[chn].phy.shu[0].ca_dll[0],
 		(0x1 << 31) | (0x1 << 30) | (0xf << 20) | (0xf << 16) |
 		(0xf << 12) | (0x1 << 10) | (0x1 << 9) | (0x1 << 4),
 		(phdet_out << 31) | (phdet_in << 30) |
@@ -147,11 +147,11 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group)
 	u8 pd_ck_sel = is_master ? 0x1 : 0x0;
 	u8 fastpj_ck_sel = is_master ? 0x0 : 0x1;
 
-	clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[1],
+	clrsetbits32(&ch[chn].phy.shu[0].ca_dll[1],
 		(0x1 << 2) | (0x1 << 0),
 		(pd_ck_sel << 2) | (fastpj_ck_sel << 0));
 
-	clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6],
+	clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[6],
 		0x1 << 7, (is_master ? 0x1 : 0x0) << 7);
 
 	struct reg_value regs_bak[] = {
@@ -164,86 +164,86 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group)
 		regs_bak[i].value = read32(regs_bak[i].addr);
 
 	for (size_t b = 0; b < 2; b++)
-		setbits_le32(&ch[chn].phy.b[b].dq[7],
+		setbits32(&ch[chn].phy.b[b].dq[7],
 			0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0);
-	setbits_le32(&ch[chn].phy.ca_cmd[7], 0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0);
-	setbits_le32(&ch[chn].phy.ca_cmd[2], 0x1 << 21);
+	setbits32(&ch[chn].phy.ca_cmd[7], 0x1 << 6 | 0x1 << 4 | 0x1 << 2 | 0x1 << 0);
+	setbits32(&ch[chn].phy.ca_cmd[2], 0x1 << 21);
 
 	/* 26M */
 	SET32_BITFIELDS(&ch[chn].phy.misc_cg_ctrl0, MISC_CG_CTRL0_CLK_MEM_SEL, 0);
 
 	/* MID FINE_TUNE */
-	clrbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], (0x1 << 26) | (0x1 << 27));
-	clrbits_le32(&ch[chn].phy.shu[0].b[1].dq[6], (0x1 << 26) | (0x1 << 27));
-	clrbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], (0x1 << 26) | (0x1 << 27));
-	clrbits_le32(&ch[chn].phy.pll4, (0x1 << 16) | (0x1 << 22));
+	clrbits32(&ch[chn].phy.shu[0].b[0].dq[6], (0x1 << 26) | (0x1 << 27));
+	clrbits32(&ch[chn].phy.shu[0].b[1].dq[6], (0x1 << 26) | (0x1 << 27));
+	clrbits32(&ch[chn].phy.shu[0].ca_cmd[6], (0x1 << 26) | (0x1 << 27));
+	clrbits32(&ch[chn].phy.pll4, (0x1 << 16) | (0x1 << 22));
 
 	/* PLL */
-	clrbits_le32(&ch[chn].phy.pll1, 0x1 << 31);
-	clrbits_le32(&ch[chn].phy.pll2, 0x1 << 31);
+	clrbits32(&ch[chn].phy.pll1, 0x1 << 31);
+	clrbits32(&ch[chn].phy.pll2, 0x1 << 31);
 
 	/* DLL */
-	clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 0);
-	clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 0);
-	clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 0);
-	setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2],
+	clrbits32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 0);
+	clrbits32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 0);
+	clrbits32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 0);
+	setbits32(&ch[chn].phy.b[0].dll_fine_tune[2],
 		(0x1 << 10) | (0x1 << 11) | (0x1 << 13) | (0x1 << 14) |
 		(0x1 << 15) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31));
-	setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2],
+	setbits32(&ch[chn].phy.b[1].dll_fine_tune[2],
 		(0x1 << 10) | (0x1 << 11) | (0x1 << 13) | (0x1 << 14) |
 		(0x1 << 15) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31));
-	setbits_le32(&ch[chn].phy.ca_dll_fine_tune[2],
+	setbits32(&ch[chn].phy.ca_dll_fine_tune[2],
 		(0x1 << 10) | (0x1 << 11) | (0x1 << 13) | (0x1 << 15) |
 		(0x1 << 16) | (0x1 << 17) | (0x1 << 19) | (0x1 << 27) | (0x1 << 31));
 
 	/* RESETB */
-	clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 3);
-	clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 3);
-	clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 3);
+	clrbits32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 3);
+	clrbits32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 3);
+	clrbits32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 3);
 
 	udelay(1);
 
 	/* MPLL 52M */
-	clrsetbits_le32(&ch[chn].phy.shu[0].pll[8],
+	clrsetbits32(&ch[chn].phy.shu[0].pll[8],
 		(0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18));
-	clrsetbits_le32(&ch[chn].phy.shu[0].pll[10],
+	clrsetbits32(&ch[chn].phy.shu[0].pll[10],
 		(0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18));
-	clrsetbits_le32(&ch[chn].phy.shu[0].pll[5],
+	clrsetbits32(&ch[chn].phy.shu[0].pll[5],
 		(0xffff << 16) | 0x1 << 0, sdm_pcw << 16);
-	clrsetbits_le32(&ch[chn].phy.shu[0].pll[7],
+	clrsetbits32(&ch[chn].phy.shu[0].pll[7],
 		(0xffff << 16) | 0x1 << 0, sdm_pcw << 16);
 
-	setbits_le32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 1);
-	setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 1);
-	setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 1);
+	setbits32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 1);
+	setbits32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 1);
+	setbits32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 1);
 
-	clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[1], 0x1 << 11);
-	clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 19);
-	clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 19);
+	clrbits32(&ch[chn].phy.ca_dll_fine_tune[1], 0x1 << 11);
+	clrbits32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 19);
+	clrbits32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 19);
 
-	clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dq[6],
+	clrsetbits32(&ch[chn].phy.shu[0].b[0].dq[6],
 		(0x3 << 22) | (0x3 << 24) | (0x3 << 28),
 		(mid_cap_sel << 22) | (vth_sel << 24) | (cap_sel << 28));
-	clrsetbits_le32(&ch[chn].phy.shu[0].b[1].dq[6],
+	clrsetbits32(&ch[chn].phy.shu[0].b[1].dq[6],
 		(0x3 << 22) | (0x3 << 24) | (0x3 << 28),
 		(mid_cap_sel << 22) | (vth_sel << 24) | (cap_sel << 28));
-	clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6],
+	clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[6],
 		(0x3 << 22) | (0x3 << 24) | (0x3 << 28),
 		(mid_cap_sel << 22) | (vth_sel << 24) | (cap_sel << 28));
 
 	/* RESETB */
-	setbits_le32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 3);
-	setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 3);
-	setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 3);
+	setbits32(&ch[chn].phy.ca_dll_fine_tune[0], 0x1 << 3);
+	setbits32(&ch[chn].phy.b[0].dll_fine_tune[0], 0x1 << 3);
+	setbits32(&ch[chn].phy.b[1].dll_fine_tune[0], 0x1 << 3);
 	udelay(1);
 
 	/* PLL EN */
-	setbits_le32(&ch[chn].phy.pll1, 0x1 << 31);
-	setbits_le32(&ch[chn].phy.pll2, 0x1 << 31);
+	setbits32(&ch[chn].phy.pll1, 0x1 << 31);
+	setbits32(&ch[chn].phy.pll2, 0x1 << 31);
 	udelay(100);
 
 	/* MIDPI Init 1 */
-	setbits_le32(&ch[chn].phy.pll4, (0x1 << 16) | (0x1 << 22));
+	setbits32(&ch[chn].phy.pll4, (0x1 << 16) | (0x1 << 22));
 	udelay(1);
 
 	/* MIDPI Init 2 */
@@ -261,50 +261,50 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group)
 	u32 dq6_clear = (0x1 << 26) | (0x1 << 27);
 	u32 dq6_set = (midpi_en << 26) | (midpi_ckdiv4_en << 27);
 
-	clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], dq6_clear, dq6_set);
-	clrsetbits_le32(&ch[chn].phy.shu[0].b[1].dq[6], dq6_clear, dq6_set);
-	clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], dq6_clear, dq6_set);
+	clrsetbits32(&ch[chn].phy.shu[0].b[0].dq[6], dq6_clear, dq6_set);
+	clrsetbits32(&ch[chn].phy.shu[0].b[1].dq[6], dq6_clear, dq6_set);
+	clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[6], dq6_clear, dq6_set);
 
 	udelay(1);
-	clrsetbits_le32(&ch[chn].phy.ca_dll_fine_tune[3], 0x1 << 19,
+	clrsetbits32(&ch[chn].phy.ca_dll_fine_tune[3], 0x1 << 19,
 		(0x1 << 13) | (0x1 << 15) | (0x1 << 16) | (0x1 << 17) |
 		((chn ? 0 : 1) << 19));
-	setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[3],
+	setbits32(&ch[chn].phy.b[0].dll_fine_tune[3],
 		(0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) |
 		(0x1 << 17));
-	setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[3],
+	setbits32(&ch[chn].phy.b[1].dll_fine_tune[3],
 		(0x1 << 11) | (0x1 << 13) | (0x1 << 14) | (0x1 << 15) |
 		(0x1 << 17));
 
-	clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[2],
+	clrbits32(&ch[chn].phy.ca_dll_fine_tune[2],
 		(0x1 << 10) | (0x1 << 13) |
 		(0x1 << 15) | (0x1 << 16) | (0x1 << 17) |
 		(0x1 << 19) | (0x1 << 27) | (0x1 << 31));
-	clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2],
+	clrbits32(&ch[chn].phy.b[0].dll_fine_tune[2],
 		(0x1 << 10) | (0x1 << 13) | (0x1 << 14) |
 		(0x1 << 15)  | (0x1 << 17) |
 		(0x1 << 19) | (0x1 << 27) | (0x1 << 31));
-	clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2],
+	clrbits32(&ch[chn].phy.b[1].dll_fine_tune[2],
 		(0x1 << 10) | (0x1 << 13) |
 		(0x1 << 14) | (0x1 << 15) | (0x1 << 17) |
 		(0x1 << 19) | (0x1 << 27) | (0x1 << 31));
 
-	setbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 11);
-	clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 11);
-	clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 11);
+	setbits32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 11);
+	clrbits32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 11);
+	clrbits32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 11);
 	udelay(2);
 
-	setbits_le32(&ch[chn].phy.misc_cg_ctrl0, 0x1 << 4);
+	setbits32(&ch[chn].phy.misc_cg_ctrl0, 0x1 << 4);
 	udelay(1);
 
 	/* DLL */
-	setbits_le32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 0);
+	setbits32(&ch[chn].phy.ca_dll_fine_tune[2], 0x1 << 0);
 	udelay(1);
-	setbits_le32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 0);
-	setbits_le32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 0);
+	setbits32(&ch[chn].phy.b[0].dll_fine_tune[2], 0x1 << 0);
+	setbits32(&ch[chn].phy.b[1].dll_fine_tune[2], 0x1 << 0);
 	udelay(1);
 
-	clrbits_le32(&ch[chn].phy.ca_cmd[2], 0x1 << 21);
+	clrbits32(&ch[chn].phy.ca_cmd[2], 0x1 << 21);
 	for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
 		write32(regs_bak[i].addr, regs_bak[i].value);
 
@@ -312,18 +312,18 @@ static void ddr_phy_pll_setting(u8 chn, u8 freq_group)
 	cke_fix_onoff(CKE_DYNAMIC, CHANNEL_B);
 
 	if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600) {
-		setbits_le32(&ch[chn].phy.shu[0].pll[5], 0x1 << 0);
-		setbits_le32(&ch[chn].phy.shu[0].pll[7], 0x1 << 0);
-		setbits_le32(&ch[chn].phy.shu[0].pll[14], 0x1 << 1);
-		setbits_le32(&ch[chn].phy.shu[0].pll20, 0x1 << 1);
-		clrsetbits_le32(&ch[chn].phy.shu[0].pll[14],
-				0xffff << 16, 0x0208 << 16);
-		clrsetbits_le32(&ch[chn].phy.shu[0].pll20,
-				0xffff << 16, 0x0208 << 16);
-		clrsetbits_le32(&ch[chn].phy.shu[0].pll[15],
-				0xffffffff << 0, delta << 16);
-		clrsetbits_le32(&ch[chn].phy.shu[0].pll21,
-				0xffffffff << 0, delta << 16);
+		setbits32(&ch[chn].phy.shu[0].pll[5], 0x1 << 0);
+		setbits32(&ch[chn].phy.shu[0].pll[7], 0x1 << 0);
+		setbits32(&ch[chn].phy.shu[0].pll[14], 0x1 << 1);
+		setbits32(&ch[chn].phy.shu[0].pll20, 0x1 << 1);
+		clrsetbits32(&ch[chn].phy.shu[0].pll[14],
+			     0xffff << 16, 0x0208 << 16);
+		clrsetbits32(&ch[chn].phy.shu[0].pll20,
+			     0xffff << 16, 0x0208 << 16);
+		clrsetbits32(&ch[chn].phy.shu[0].pll[15],
+			     0xffffffff << 0, delta << 16);
+		clrsetbits32(&ch[chn].phy.shu[0].pll21,
+			     0xffffffff << 0, delta << 16);
 	}
 }
 
@@ -337,17 +337,17 @@ static void dramc_gating_mode(u8 mode)
 	}
 
 	for (u8 b = 0; b < 2; b++) {
-		clrsetbits_le32(&ch[0].phy.b[b].dq[6], 0x3 << 14, vref_sel << 14);
-		setbits_le32(&ch[0].phy.b[b].dq[9], 0x1 << 5);
+		clrsetbits32(&ch[0].phy.b[b].dq[6], 0x3 << 14, vref_sel << 14);
+		setbits32(&ch[0].phy.b[b].dq[9], 0x1 << 5);
 	}
 
-	clrsetbits_le32(&ch[0].ao.stbcal1, 0x1 << 5, burst << 5);
-	setbits_le32(&ch[0].ao.stbcal, 0x1 << 30);
+	clrsetbits32(&ch[0].ao.stbcal1, 0x1 << 5, burst << 5);
+	setbits32(&ch[0].ao.stbcal, 0x1 << 30);
 
 	for (u8 b = 0; b < 2; b++) {
-		clrbits_le32(&ch[0].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0));
+		clrbits32(&ch[0].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0));
 		udelay(1);
-		setbits_le32(&ch[0].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0));
+		setbits32(&ch[0].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0));
 	}
 }
 
@@ -360,196 +360,196 @@ static void update_initial_settings(u8 freq_group)
 		rx_vref = 0xb;
 
 	if (operate_fsp == FSP_1) {
-		setbits_le32(&ch[0].ao.shu[0].odtctrl, 0x1 << 0);
-		setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15);
-		setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15);
+		setbits32(&ch[0].ao.shu[0].odtctrl, 0x1 << 0);
+		setbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15);
+		setbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15);
 	} else {
-		clrbits_le32(&ch[0].ao.shu[0].odtctrl, 0x1 << 0);
-		clrbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15);
-		clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15);
+		clrbits32(&ch[0].ao.shu[0].odtctrl, 0x1 << 0);
+		clrbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15);
+		clrbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15);
 	}
 
 	for (size_t b = 0; b < 2; b++)
 		for (size_t r = 0; r < 2; r++)
-			clrbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2],
+			clrbits32(&ch[0].phy.r[r].b[b].rxdvs[2],
 				 (0x1 << 23) | (0x1 << 28) | (0x3 << 30));
-	clrbits_le32(&ch[0].phy.shu[0].ca_cmd[7], 0xf << 0);
-
-	setbits_le32(&ch[0].phy.ca_cmd[3], 0x1 << 10);
-	setbits_le32(&ch[0].phy.ca_cmd[10], 0x1 << 5);
-	clrsetbits_le32(&ch[0].phy.ca_cmd[6], 0x3 << 14, 0x1 << 14);
-	setbits_le32(&ch[0].phy.b[0].dq[3], 0x7 << 5);
-	setbits_le32(&ch[0].phy.b[1].dq[3], 0x7 << 5);
-	setbits_le32(&ch[0].phy.ca_cmd[3], (0x1 << 5) | (0x1 << 7));
-	clrbits_le32(&ch[0].phy.b[0].dq[3], 0x1 << 1);
-	clrbits_le32(&ch[0].phy.b[1].dq[3], 0x1 << 1);
-	setbits_le32(&ch[0].phy.b[0].dq[5], 0x1 << 31);
-	setbits_le32(&ch[0].phy.b[1].dq[5], 0x1 << 31);
-	setbits_le32(&ch[0].phy.ca_cmd[5], 0x1 << 31);
-
-	clrsetbits_le32(&ch[0].phy.ca_cmd[6], 0xf << 16, 0x3 << 16);
-	clrsetbits_le32(&ch[0].phy.misc_imp_ctrl0, (0x1 << 5) | (0x1 << 6),
+	clrbits32(&ch[0].phy.shu[0].ca_cmd[7], 0xf << 0);
+
+	setbits32(&ch[0].phy.ca_cmd[3], 0x1 << 10);
+	setbits32(&ch[0].phy.ca_cmd[10], 0x1 << 5);
+	clrsetbits32(&ch[0].phy.ca_cmd[6], 0x3 << 14, 0x1 << 14);
+	setbits32(&ch[0].phy.b[0].dq[3], 0x7 << 5);
+	setbits32(&ch[0].phy.b[1].dq[3], 0x7 << 5);
+	setbits32(&ch[0].phy.ca_cmd[3], (0x1 << 5) | (0x1 << 7));
+	clrbits32(&ch[0].phy.b[0].dq[3], 0x1 << 1);
+	clrbits32(&ch[0].phy.b[1].dq[3], 0x1 << 1);
+	setbits32(&ch[0].phy.b[0].dq[5], 0x1 << 31);
+	setbits32(&ch[0].phy.b[1].dq[5], 0x1 << 31);
+	setbits32(&ch[0].phy.ca_cmd[5], 0x1 << 31);
+
+	clrsetbits32(&ch[0].phy.ca_cmd[6], 0xf << 16, 0x3 << 16);
+	clrsetbits32(&ch[0].phy.misc_imp_ctrl0, (0x1 << 5) | (0x1 << 6),
 		(0x1 << 5) | (0x0 << 6));
-	setbits_le32(&ch[0].phy.b[0].dq[6], 0x1 << 9);
-	setbits_le32(&ch[0].phy.b[1].dq[6], 0x1 << 9);
-	setbits_le32(&ch[0].phy.ca_cmd[6], 0x1 << 9);
-	clrsetbits_le32(&ch[0].phy.b[0].dq[6], 0x3 << 0, 0x1 << 0);
-	clrsetbits_le32(&ch[0].phy.b[1].dq[6], 0x1 << 0, 0x1 << 0);
-	clrsetbits_le32(&ch[0].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0);
-
-	setbits_le32(&ch[0].phy.ca_cmd[6], 0x1 << 6);
-	setbits_le32(&ch[0].phy.b[0].dq[6], 0x1 << 3);
-	setbits_le32(&ch[0].phy.b[1].dq[6], 0x1 << 3);
-	setbits_le32(&ch[0].phy.ca_cmd[6], 0x1 << 3);
-	setbits_le32(&ch[0].phy.b[0].dq[6], 0x1 << 5);
-	setbits_le32(&ch[0].phy.b[1].dq[6], 0x1 << 5);
-	setbits_le32(&ch[0].phy.ca_cmd[6], 0x1 << 5);
+	setbits32(&ch[0].phy.b[0].dq[6], 0x1 << 9);
+	setbits32(&ch[0].phy.b[1].dq[6], 0x1 << 9);
+	setbits32(&ch[0].phy.ca_cmd[6], 0x1 << 9);
+	clrsetbits32(&ch[0].phy.b[0].dq[6], 0x3 << 0, 0x1 << 0);
+	clrsetbits32(&ch[0].phy.b[1].dq[6], 0x1 << 0, 0x1 << 0);
+	clrsetbits32(&ch[0].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0);
+
+	setbits32(&ch[0].phy.ca_cmd[6], 0x1 << 6);
+	setbits32(&ch[0].phy.b[0].dq[6], 0x1 << 3);
+	setbits32(&ch[0].phy.b[1].dq[6], 0x1 << 3);
+	setbits32(&ch[0].phy.ca_cmd[6], 0x1 << 3);
+	setbits32(&ch[0].phy.b[0].dq[6], 0x1 << 5);
+	setbits32(&ch[0].phy.b[1].dq[6], 0x1 << 5);
+	setbits32(&ch[0].phy.ca_cmd[6], 0x1 << 5);
 
 	for (u8 b = 0; b < 2; b++) {
-		clrsetbits_le32(&ch[0].phy.shu[0].b[b].dq[5], 0x3f << 0, rx_vref << 0);
-		clrsetbits_le32(&ch[0].phy.b[b].dq[5], 0x3f << 8, rx_vref << 8);
+		clrsetbits32(&ch[0].phy.shu[0].b[b].dq[5], 0x3f << 0, rx_vref << 0);
+		clrsetbits32(&ch[0].phy.b[b].dq[5], 0x3f << 8, rx_vref << 8);
 	}
 
-	setbits_le32(&ch[0].phy.b[0].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
-	setbits_le32(&ch[0].phy.b[1].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
-	setbits_le32(&ch[0].phy.ca_cmd[9], (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
+	setbits32(&ch[0].phy.b[0].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
+	setbits32(&ch[0].phy.b[1].dq[8], (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
+	setbits32(&ch[0].phy.ca_cmd[9], (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
 	dramc_gating_mode(1);
 
-	setbits_le32(&ch[0].phy.ca_cmd[8], 0x1 << 19);
-	clrbits_le32(&ch[0].phy.ca_cmd[8], 0x1 << 18);
-	clrsetbits_le32(&ch[0].ao.shu[0].misc, 0xf << 0, 0x2 << 0);
-	clrsetbits_le32(&ch[0].ao.shu[0].dqsg, (0x3f << 20) | (0x1 << 16),
+	setbits32(&ch[0].phy.ca_cmd[8], 0x1 << 19);
+	clrbits32(&ch[0].phy.ca_cmd[8], 0x1 << 18);
+	clrsetbits32(&ch[0].ao.shu[0].misc, 0xf << 0, 0x2 << 0);
+	clrsetbits32(&ch[0].ao.shu[0].dqsg, (0x3f << 20) | (0x1 << 16),
 		(0x2a << 20) | (0x1 << 16));
 
-	clrbits_le32(&ch[0].phy.shu[0].b[0].dq[5], 0x3f << 8);
-	clrbits_le32(&ch[0].phy.shu[0].b[1].dq[5], 0x3f << 8);
-	clrbits_le32(&ch[0].phy.shu[0].ca_cmd[5], 0x3f << 8);
+	clrbits32(&ch[0].phy.shu[0].b[0].dq[5], 0x3f << 8);
+	clrbits32(&ch[0].phy.shu[0].b[1].dq[5], 0x3f << 8);
+	clrbits32(&ch[0].phy.shu[0].ca_cmd[5], 0x3f << 8);
 
 	dramc_set_broadcast(DRAMC_BROADCAST_OFF);
 	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		clrbits_le32(&ch[chn].phy.shu[0].b[0].dq[6], 0x3f << 0);
-		clrbits_le32(&ch[chn].phy.shu[0].b[1].dq[6], 0x3f << 0);
-		clrbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0x3f << 0);
+		clrbits32(&ch[chn].phy.shu[0].b[0].dq[6], 0x3f << 0);
+		clrbits32(&ch[chn].phy.shu[0].b[1].dq[6], 0x3f << 0);
+		clrbits32(&ch[chn].phy.shu[0].ca_cmd[6], 0x3f << 0);
 	}
 	dramc_set_broadcast(DRAMC_BROADCAST_ON);
 
 	/* IMP Tracking Init Settings */
-	clrsetbits_le32(&ch[0].ao.shu[0].impcal1,
+	clrsetbits32(&ch[0].ao.shu[0].impcal1,
 		(0x7 << 0) | (0x7 << 17) | (0xff << 20) | (0xf << 28),
 		(0x4 << 0) | (0x4 << 17) | (0x10 << 20) | (0x8 << 28));
 
-	setbits_le32(&ch[0].ao.srefctrl, 0xf << 12);
-	setbits_le32(&ch[0].ao.pre_tdqsck[0], 0x1 << 17);
-	setbits_le32(&ch[0].ao.shu[0].misc, 0xf << 12);
-	clrsetbits_le32(&ch[0].phy.shu[0].b[0].dq[8],
+	setbits32(&ch[0].ao.srefctrl, 0xf << 12);
+	setbits32(&ch[0].ao.pre_tdqsck[0], 0x1 << 17);
+	setbits32(&ch[0].ao.shu[0].misc, 0xf << 12);
+	clrsetbits32(&ch[0].phy.shu[0].b[0].dq[8],
 		(0xffff << 0) | (0x1 << 15) | (0x3ff << 22),
 		(0x7fff << 0) | (0x0 << 15) | (0x3ff << 22));
-	clrsetbits_le32(&ch[0].phy.shu[0].b[1].dq[8],
+	clrsetbits32(&ch[0].phy.shu[0].b[1].dq[8],
 		(0xffff << 0) | (0x1 << 15) | (0x3ff << 22),
 		(0x7fff << 0) | (0x0 << 15) | (0x3ff << 22));
-	clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[8],
+	clrsetbits32(&ch[0].phy.shu[0].ca_cmd[8],
 		(0xffff << 0) | (0x1 << 15) | (0x3ff << 22),
 		(0x7fff << 0) | (0x0 << 15) | (0x3ff << 22));
-	setbits_le32(&ch[0].phy.misc_ctrl3, 0x1 << 26);
-	clrbits_le32(&ch[0].phy.shu[0].b[0].dq[7], (0xf << 8) | (0x1 << 12) | (0x1 << 13));
-	clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7], (0xf << 8) | (0x1 << 12) | (0x1 << 13));
-	clrsetbits_le32(&ch[0].ao.clkar, (0xffff << 0) | (0x1 << 15),
+	setbits32(&ch[0].phy.misc_ctrl3, 0x1 << 26);
+	clrbits32(&ch[0].phy.shu[0].b[0].dq[7], (0xf << 8) | (0x1 << 12) | (0x1 << 13));
+	clrbits32(&ch[0].phy.shu[0].b[1].dq[7], (0xf << 8) | (0x1 << 12) | (0x1 << 13));
+	clrsetbits32(&ch[0].ao.clkar, (0xffff << 0) | (0x1 << 15),
 		(0x7fff << 0) | (0x1 << 15));
 
-	clrbits_le32(&ch[0].ao.shu[0].dqsg_retry, 0x1 << 29);
-	clrbits_le32(&ch[0].ao.write_lev, 0x1 << 2);
-	setbits_le32(&ch[0].ao.dummy_rd, 0x1 << 24);
-	clrbits_le32(&ch[0].ao.stbcal2, (0x1 << 0) | (0x1 << 1));
-	setbits_le32(&ch[0].ao.eyescan, (0x1 << 8) | (0x1 << 9) | (0x1 << 10));
-	setbits_le32(&ch[0].ao.shu[0].odtctrl, (0x1 << 2) | (0x1 << 3));
-
-	setbits_le32(&ch[0].phy.shu[0].b[0].dll[0], 0x1 << 0);
-	setbits_le32(&ch[0].phy.shu[0].b[1].dll[0], 0x1 << 0);
-	setbits_le32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 21);
-
-	setbits_le32(&ch[0].ao.perfctl0, (0x1 << 15) | (0x1 << 19) | (0x1 << 26));
-	setbits_le32(&ch[0].ao.srefctrl, 0x1 << 22);
-	clrsetbits_le32(&ch[0].ao.shuctrl1, 0xff << 0, 0x1a << 0);
-	setbits_le32(&ch[0].phy.b[0].dq[6], (0x1 << 7) | (0x1 << 12));
-	setbits_le32(&ch[0].phy.b[1].dq[6], (0x1 << 7) | (0x1 << 12));
-	setbits_le32(&ch[0].phy.ca_cmd[6], (0x1 << 7) | (0x1 << 12));
-	setbits_le32(&ch[0].ao.stbcal2, 0x1 << 16);
-	clrsetbits_le32(&ch[0].phy.shu[0].b[0].dq[7],
+	clrbits32(&ch[0].ao.shu[0].dqsg_retry, 0x1 << 29);
+	clrbits32(&ch[0].ao.write_lev, 0x1 << 2);
+	setbits32(&ch[0].ao.dummy_rd, 0x1 << 24);
+	clrbits32(&ch[0].ao.stbcal2, (0x1 << 0) | (0x1 << 1));
+	setbits32(&ch[0].ao.eyescan, (0x1 << 8) | (0x1 << 9) | (0x1 << 10));
+	setbits32(&ch[0].ao.shu[0].odtctrl, (0x1 << 2) | (0x1 << 3));
+
+	setbits32(&ch[0].phy.shu[0].b[0].dll[0], 0x1 << 0);
+	setbits32(&ch[0].phy.shu[0].b[1].dll[0], 0x1 << 0);
+	setbits32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 21);
+
+	setbits32(&ch[0].ao.perfctl0, (0x1 << 15) | (0x1 << 19) | (0x1 << 26));
+	setbits32(&ch[0].ao.srefctrl, 0x1 << 22);
+	clrsetbits32(&ch[0].ao.shuctrl1, 0xff << 0, 0x1a << 0);
+	setbits32(&ch[0].phy.b[0].dq[6], (0x1 << 7) | (0x1 << 12));
+	setbits32(&ch[0].phy.b[1].dq[6], (0x1 << 7) | (0x1 << 12));
+	setbits32(&ch[0].phy.ca_cmd[6], (0x1 << 7) | (0x1 << 12));
+	setbits32(&ch[0].ao.stbcal2, 0x1 << 16);
+	clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7],
 		(0x7 << 29) | (0x1 << 28) | (0x7 << 25) | (0x1 << 24),
 		(0x0 << 29) | (0x1 << 28) | (0x1 << 25) | (0x1 << 24));
-	clrsetbits_le32(&ch[0].phy.shu[0].b[1].dq[7],
+	clrsetbits32(&ch[0].phy.shu[0].b[1].dq[7],
 		(0x7 << 29) | (0x1 << 28) | (0x7 << 25) | (0x1 << 24),
 		(0x0 << 29) | (0x1 << 28) | (0x1 << 25) | (0x1 << 24));
 
 	/* Disable RODT tracking */
-	clrbits_le32(&ch[0].ao.shu[0].rodtenstb, 0x1 << 0);
+	clrbits32(&ch[0].ao.shu[0].rodtenstb, 0x1 << 0);
 
 	/* Rx Gating tracking settings */
-	clrsetbits_le32(&ch[0].ao.shu[0].dqsg,
+	clrsetbits32(&ch[0].ao.shu[0].dqsg,
 		(0x1 << 11) | (0xf << 12), (0x1 << 11) | (0x9 << 12));
-	clrbits_le32(&ch[0].ao.shu[0].rk[0].dqscal, (0x1 << 7) | (0x1 << 15));
-	clrbits_le32(&ch[0].ao.shu[0].rk[1].dqscal, (0x1 << 7) | (0x1 << 15));
-	clrsetbits_le32(&ch[0].ao.shu[0].stbcal,
+	clrbits32(&ch[0].ao.shu[0].rk[0].dqscal, (0x1 << 7) | (0x1 << 15));
+	clrbits32(&ch[0].ao.shu[0].rk[1].dqscal, (0x1 << 7) | (0x1 << 15));
+	clrsetbits32(&ch[0].ao.shu[0].stbcal,
 		(0x7 << 4) | (0x1 << 8), (0x1 << 4) | (0x1 << 8));
 
-	clrsetbits_le32(&ch[0].phy.b[0].dq[9], 0xff << 8, 0x4 << 8);
-	clrsetbits_le32(&ch[0].phy.b[1].dq[9], 0xff << 8, 0x4 << 8);
-	clrbits_le32(&ch[0].phy.ca_cmd[10], 0xff << 8);
+	clrsetbits32(&ch[0].phy.b[0].dq[9], 0xff << 8, 0x4 << 8);
+	clrsetbits32(&ch[0].phy.b[1].dq[9], 0xff << 8, 0x4 << 8);
+	clrbits32(&ch[0].phy.ca_cmd[10], 0xff << 8);
 
-	setbits_le32(&ch[0].phy.shu[0].b[0].dq[8], 0x1 << 24);
-	setbits_le32(&ch[0].phy.shu[0].b[1].dq[8], 0x1 << 24);
+	setbits32(&ch[0].phy.shu[0].b[0].dq[8], 0x1 << 24);
+	setbits32(&ch[0].phy.shu[0].b[1].dq[8], 0x1 << 24);
 
 	/* Enable WDQS */
-	clrsetbits_le32(&ch[0].phy.shu[0].b[0].dll[1],
+	clrsetbits32(&ch[0].phy.shu[0].b[0].dll[1],
 		(0x1 << 10) | (0x1 << 16) | (0x1 << 17),
 		(0x1 << 10) | (!operate_fsp << 16) | (0x1 << 17));
-	clrsetbits_le32(&ch[0].phy.shu[0].b[1].dll[1],
+	clrsetbits32(&ch[0].phy.shu[0].b[1].dll[1],
 		(0x1 << 10) | (0x1 << 16) | (0x1 << 17),
 		(0x1 << 10) | (!operate_fsp << 16) | (0x1 << 17));
-	setbits_le32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x1 << 30) | (0x1 << 31));
-	setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15);
-	setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15);
-	setbits_le32(&ch[0].ao.drsctrl, 0x1 << 19);
-	setbits_le32(&ch[0].ao.refctrl0, 0x1 << 28);
-	setbits_le32(&ch[0].ao.zqcs, 0x1 << 19);
-	setbits_le32(&ch[0].ao.dummy_rd, 0x3 << 26);
-	setbits_le32(&ch[0].ao.shuctrl2, 0x1 << 8);
-	clrsetbits_le32(&ch[0].ao.shuctrl3, 0xff << 24, 0xb << 24);
-	setbits_le32(&ch[0].phy.misc_ctrl3, 0x1 << 27);
-	setbits_le32(&ch[0].phy.b[0].dll_fine_tune[1], 0x3 << 20);
-	setbits_le32(&ch[0].phy.b[1].dll_fine_tune[1], 0x3 << 20);
-	setbits_le32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 20);
-	clrbits_le32(&ch[0].phy.misc_ctrl0, 0x1 << 27);
-	setbits_le32(&ch[0].phy.misc_rxdvs[2], 0x1 << 8);
-	setbits_le32(&ch[0].ao.clkctrl, 0x1 << 7);
-	setbits_le32(&ch[0].ao.refctrl1, 0x1 << 7);
-	clrsetbits_le32(&ch[0].ao.shuctrl, (0x1 << 2) | (0x3 << 6) | (0x3 << 26),
+	setbits32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x1 << 30) | (0x1 << 31));
+	setbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15);
+	setbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15);
+	setbits32(&ch[0].ao.drsctrl, 0x1 << 19);
+	setbits32(&ch[0].ao.refctrl0, 0x1 << 28);
+	setbits32(&ch[0].ao.zqcs, 0x1 << 19);
+	setbits32(&ch[0].ao.dummy_rd, 0x3 << 26);
+	setbits32(&ch[0].ao.shuctrl2, 0x1 << 8);
+	clrsetbits32(&ch[0].ao.shuctrl3, 0xff << 24, 0xb << 24);
+	setbits32(&ch[0].phy.misc_ctrl3, 0x1 << 27);
+	setbits32(&ch[0].phy.b[0].dll_fine_tune[1], 0x3 << 20);
+	setbits32(&ch[0].phy.b[1].dll_fine_tune[1], 0x3 << 20);
+	setbits32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 20);
+	clrbits32(&ch[0].phy.misc_ctrl0, 0x1 << 27);
+	setbits32(&ch[0].phy.misc_rxdvs[2], 0x1 << 8);
+	setbits32(&ch[0].ao.clkctrl, 0x1 << 7);
+	setbits32(&ch[0].ao.refctrl1, 0x1 << 7);
+	clrsetbits32(&ch[0].ao.shuctrl, (0x1 << 2) | (0x3 << 6) | (0x3 << 26),
 		(0x0 << 2) | (0x3 << 6) | (0x3 << 26));
-	setbits_le32(&ch[0].ao.shuctrl2, (0x1 << 31) | (0x3 << 10));
-	clrbits_le32(&ch[0].ao.stbcal2, 0xf << 4);
-	clrbits_le32(&ch[0].ao.pre_tdqsck[0], 0x3 << 19);
+	setbits32(&ch[0].ao.shuctrl2, (0x1 << 31) | (0x3 << 10));
+	clrbits32(&ch[0].ao.stbcal2, 0xf << 4);
+	clrbits32(&ch[0].ao.pre_tdqsck[0], 0x3 << 19);
 
-	setbits_le32(&ch[0].ao.ckectrl, 0x1 << 22);
-	clrsetbits_le32(&ch[0].phy.ca_tx_mck, (0x1 << 31) | (0x1f << 21) | (0x1f << 26),
+	setbits32(&ch[0].ao.ckectrl, 0x1 << 22);
+	clrsetbits32(&ch[0].phy.ca_tx_mck, (0x1 << 31) | (0x1f << 21) | (0x1f << 26),
 		(0x1 << 31) | (0xa << 21) | (0xa << 26));
-	setbits_le32(&ch[0].ao.ckectrl, 0x1 << 23);
-	clrbits_le32(&ch[0].ao.shu[0].rodtenstb, 0x1 << 31);
+	setbits32(&ch[0].ao.ckectrl, 0x1 << 23);
+	clrbits32(&ch[0].ao.shu[0].rodtenstb, 0x1 << 31);
 }
 
 static void dramc_power_on_sequence(void)
 {
 	for (size_t chn = 0; chn < CHANNEL_MAX; chn++)
-		clrbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 13);
+		clrbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 13);
 
 	dramc_cke_fix_onoff(CHANNEL_A, false, true);
 	dramc_cke_fix_onoff(CHANNEL_B, false, true);
 
 	udelay(200);
 	for (size_t chn = 0; chn < CHANNEL_MAX; chn++)
-		setbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 13);
+		setbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 13);
 
 	for (size_t chn = 0; chn < CHANNEL_MAX; chn++)
-		setbits_le32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26);
+		setbits32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26);
 
 	udelay(2000);
 	dramc_cke_fix_onoff(CHANNEL_A, true, false);
@@ -571,22 +571,22 @@ static void ddr_phy_reserved_rg_setting(u8 freq_group)
 
 	/* fine tune */
 	for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-		clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[6], 0xffff << 6,
+		clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[6], 0xffff << 6,
 			(0x1 << 6) | ((!chn) << 7) | (hyst_sel << 8) |
 			(midpi_cap_sel << 9) | (0x1 << 10) | (0x3 << 17) | (lp3_sel << 20));
 
 	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		clrsetbits_le32(&ch[chn].phy.shu[0].ca_dll[1],
+		clrsetbits32(&ch[chn].phy.shu[0].ca_dll[1],
 			(0xf << 9) | (0x1f << 16) | (0x7ff << 21),
 			(0x1 << 8) | (0x7 << 13) | (0x4 << 16));
 
 		for (u8 b = 0; b < 2; b++) {
-			clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dq[6],
+			clrsetbits32(&ch[chn].phy.shu[0].b[b].dq[6],
 				(0x1f << 6) | (0x3f << 11) | (0x7 << 19),
 				(0x1 << 6) | (hyst_sel << 8) | (midpi_cap_sel << 9)
 				| (0x1 << 10)  | (0x3 << 17) | (lp3_sel << 20));
 
-			clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dll[1],
+			clrsetbits32(&ch[chn].phy.shu[0].b[b].dll[1],
 				(0x3 << 8) | (0x3 << 11) | (0x7 << 14) | (0x3fff << 18),
 				(0x1 << 10) | (0x1 << 13) | (0x1 << 17));
 		}
@@ -603,12 +603,12 @@ static void dramc_duty_set_clk_delay(u8 chn, s8 clkDelay)
 	revb1 = dlyb ? 1 : 0;
 
 	for (u8 r = 0; r < RANK_MAX; r++) {
-		clrsetbits_le32(&ch[chn].phy.shu[0].rk[r].ca_cmd[1],
+		clrsetbits32(&ch[chn].phy.shu[0].rk[r].ca_cmd[1],
 			(0xf << 24) | (0xf << 28), (dly << 24) | (dly << 28));
-		clrsetbits_le32(&ch[chn].phy.shu[0].rk[r].ca_cmd[0],
+		clrsetbits32(&ch[chn].phy.shu[0].rk[r].ca_cmd[0],
 			(0xf << 24) | (0xf << 28), (dlyb << 24) | (dlyb << 28));
 	}
-	clrsetbits_le32(&ch[chn].phy.shu[0].ca_cmd[3],
+	clrsetbits32(&ch[chn].phy.shu[0].ca_cmd[3],
 		(0x3 << 8), (revb0 << 8) | (revb1 << 9));
 }
 
@@ -625,11 +625,11 @@ static void dramc_duty_set_dqs_delay(u8 chn, const s8 *s_dqsDelay)
 			dlyb = (dqsDelay < 0) ? 0 : dqsDelay;
 			revb0 = dly ? 1 : 0;
 			revb1 = dlyb ? 1 : 0;
-			clrsetbits_le32(&ch[chn].phy.shu[0].rk[r].b[dqs].dq[1],
+			clrsetbits32(&ch[chn].phy.shu[0].rk[r].b[dqs].dq[1],
 				(0xf << 24) | (0xf << 28) | (0xf << 16) | (0xf << 20),
 				(dly << 24) | (dly << 28) | (dlyb << 16) | (dlyb << 20));
 		}
-	clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dll[1],
+	clrsetbits32(&ch[chn].phy.shu[0].b[0].dll[1],
 		0x3 << 8, (revb0 << 8) | (revb1 << 9));
 }
 
@@ -709,7 +709,7 @@ static u8 dramc_zq_calibration(u8 chn, u8 rank)
 	for (size_t i = 0; i < ARRAY_SIZE(regs_bak); i++)
 		regs_bak[i].value = read32(regs_bak[i].addr);
 
-	setbits_le32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26);
+	setbits32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26);
 	dramc_cke_fix_onoff(chn, true, false);
 
 	SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank);
@@ -794,7 +794,7 @@ static void dramc_mode_reg_init(u8 freq_group, struct mr_value *mr)
 
 	for (chn = 0; chn < CHANNEL_MAX; chn++) {
 		for (rank = 0; rank < 2; rank++) {
-			clrsetbits_le32(&ch[chn].ao.mrs, 0x3 << 24, rank << 24);
+			clrsetbits32(&ch[chn].ao.mrs, 0x3 << 24, rank << 24);
 
 			dramc_zq_calibration(chn, rank);
 
@@ -827,21 +827,21 @@ static void dramc_mode_reg_init(u8 freq_group, struct mr_value *mr)
 			dramc_mode_reg_write(chn, 0xd, MR13Value);
 		}
 
-		clrsetbits_le32(&ch[chn].ao.shu[0].hwset_mr13,
+		clrsetbits32(&ch[chn].ao.shu[0].hwset_mr13,
 			(0x1fff << 0) | (0xff << 16),
 			(13 << 0) | ((MR13Value | (0x1 << 3)) << 16));
-		clrsetbits_le32(&ch[chn].ao.shu[0].hwset_vrcg,
+		clrsetbits32(&ch[chn].ao.shu[0].hwset_vrcg,
 			(0x1fff << 0) | (0xff << 16),
 			(13 << 0) | ((MR13Value | (0x1 << 3)) << 16));
-		clrsetbits_le32(&ch[chn].ao.shu[0].hwset_mr2,
+		clrsetbits32(&ch[chn].ao.shu[0].hwset_mr2,
 			(0x1fff << 0) | (0xff << 16),
 			(2 << 0) | (MR02Value[operate_fsp] << 16));
 	}
 
 	mr->MR13Value = MR13Value;
 
-	clrsetbits_le32(&ch[0].ao.mrs, 0x3 << 24, RANK_0 << 24);
-	clrsetbits_le32(&ch[1].ao.mrs, 0x3 << 24, RANK_0 << 24);
+	clrsetbits32(&ch[0].ao.mrs, 0x3 << 24, RANK_0 << 24);
+	clrsetbits32(&ch[1].ao.mrs, 0x3 << 24, RANK_0 << 24);
 	dramc_set_broadcast(broadcast_bak);
 }
 
@@ -851,7 +851,7 @@ static void auto_refresh_cke_off(void)
 	dramc_set_broadcast(DRAMC_BROADCAST_OFF);
 
 	for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
-		setbits_le32(&ch[chn].ao.refctrl0, 0x1 << 29);
+		setbits32(&ch[chn].ao.refctrl0, 0x1 << 29);
 
 	udelay(3);
 	cke_fix_onoff(CKE_FIXOFF, CHANNEL_A);
@@ -862,57 +862,57 @@ static void auto_refresh_cke_off(void)
 
 static void dramc_setting_DDR1600(void)
 {
-	clrsetbits_le32(&ch[0].ao.shu[0].rankctl,
+	clrsetbits32(&ch[0].ao.shu[0].rankctl,
 		(0xf << 20) | (0xf << 24) | (0xf << 28),
 		(0x0 << 20) | (0x0 << 24) | (0x2 << 28));
-	clrbits_le32(&ch[0].ao.shu[0].ckectrl, 0x3 << 24);
-	clrbits_le32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x3 << 30));
+	clrbits32(&ch[0].ao.shu[0].ckectrl, 0x3 << 24);
+	clrbits32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x3 << 30));
 
-	clrbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15);
-	clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15);
+	clrbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15);
+	clrbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15);
 
-	clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_1600);
-	clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_1600);
-	clrsetbits_le32(&ch[0].ao.shu[0].wodt, (0x1 << 29) | (0x1 << 31),
+	clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_1600);
+	clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_1600);
+	clrsetbits32(&ch[0].ao.shu[0].wodt, (0x1 << 29) | (0x1 << 31),
 		(0x0 << 29) | (0x1 << 31));
-	clrsetbits_le32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0, 0x4 << 0);
+	clrsetbits32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0, 0x4 << 0);
 
 	for (size_t rank = 0; rank < 2; rank++) {
 		int value = ((rank == 0) ? 0x1a : 0x1e);
-		clrbits_le32(&ch[0].ao.shu[0].rk[rank].dqsien, (0x7f << 0) | (0x7f << 8));
-		clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].fine_tune,
+		clrbits32(&ch[0].ao.shu[0].rk[rank].dqsien, (0x7f << 0) | (0x7f << 8));
+		clrsetbits32(&ch[0].ao.shu[0].rk[rank].fine_tune,
 			(0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24),
 			(value << 0) | (value << 8) | (value << 16) | (value << 24));
 
-		clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[0],
+		clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[0],
 			(0x7 << 8) | (0x7 << 12) |
 			(0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28),
 			(0x2 << 8) | (0x2 << 12) |
 			(0x1 << 16) | (0x1 << 20) | (0x1 << 24) | (0x1 << 28));
-		clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[1],
+		clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[1],
 			(0x7 << 8) | (0x7 << 12) |
 			(0x7 << 16) | (0x7 << 20) | (0x7 << 24)	| (0x7 << 28),
 			(0x2 << 8) | (0x2 << 12) |
 			(0x1 << 16) | (0x1 << 20) | (0x1 << 24) | (0x1 << 28));
-		clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2],
+		clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[2],
 			0x77777777, _SELPH_DQS_BITS(0x1, 0x7));
-		clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3],
+		clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[3],
 			0x77777777, _SELPH_DQS_BITS(0x1, 0x7));
 	}
 
-	clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8),
+	clrsetbits32(&ch[0].ao.shu[0].dqsg_retry, (0x1 << 2) | (0xf << 8),
 		(0x0 << 2) | (0x3 << 8));
-	clrsetbits_le32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x4 << 20);
+	clrsetbits32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x4 << 20);
 
-	clrsetbits_le32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13),
+	clrsetbits32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13),
 			(0x2 << 4) | (0x0 << 7) | (0x0 << 13));
-	clrsetbits_le32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x4 << 20);
-	clrbits_le32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13));
+	clrsetbits32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x4 << 20);
+	clrbits32(&ch[0].phy.b[1].dq[7], (0x1 << 7) | (0x1 << 13));
 
 	for (size_t r = 0; r < 2; r++) {
 		int value = ((r == 0) ? 0x1a : 0x26);
 		for (size_t b = 0; b < 2; b++)
-			clrsetbits_le32(&ch[0].phy.shu[0].rk[r].b[b].dq[7],
+			clrsetbits32(&ch[0].phy.shu[0].rk[r].b[b].dq[7],
 				(0x3f << 8) | (0x3f << 16),
 				(value << 8) | (value << 16));
 	}
@@ -920,65 +920,65 @@ static void dramc_setting_DDR1600(void)
 
 static void dramc_setting_DDR2400(void)
 {
-	clrsetbits_le32(&ch[0].ao.shu[0].rankctl,
+	clrsetbits32(&ch[0].ao.shu[0].rankctl,
 		(0xf << 20) | (0xf << 24) | (0xf << 28),
 		(0x2 << 20) | (0x2 << 24) | (0x4 << 28));
-	clrsetbits_le32(&ch[0].ao.shu[0].ckectrl, 0x3 << 24, 0x3 << 24);
-	setbits_le32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x1 << 30) | (0x1 << 31));
+	clrsetbits32(&ch[0].ao.shu[0].ckectrl, 0x3 << 24, 0x3 << 24);
+	setbits32(&ch[0].ao.shu[0].odtctrl, (0x1 << 0) | (0x1 << 30) | (0x1 << 31));
 
-	setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15);
-	setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15);
+	setbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15);
+	setbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15);
 
-	clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_2400);
-	clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_2400);
-	clrsetbits_le32(&ch[0].ao.shu[0].wodt,
+	clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_2400);
+	clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_2400);
+	clrsetbits32(&ch[0].ao.shu[0].wodt,
 		(0x1 << 29) | (0x1 << 31), (0x1 << 29) | (0x0 << 31));
-	clrsetbits_le32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0, 0x7 << 0);
+	clrsetbits32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0, 0x7 << 0);
 
 	for (size_t rank = 0; rank < 2; rank++) {
 		int value = ((rank == 0) ? 0x19 : 0x1f);
-		clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].dqsien,
+		clrsetbits32(&ch[0].ao.shu[0].rk[rank].dqsien,
 			(0x7f << 0) | (0x7f << 8), (value << 0) | (value  << 8));
-		clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].fine_tune,
+		clrsetbits32(&ch[0].ao.shu[0].rk[rank].fine_tune,
 			(0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24),
 			(0x14 << 0) | (0x14 << 8) | (0x14 << 16) | (0x14 << 24));
 
-		clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[0],
+		clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[0],
 			(0x7 << 8) | (0x7 << 12) |
 			(0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28),
 			(0x3 << 8) | (0x3 << 12) |
 			(0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28));
-		clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[1],
+		clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[1],
 			(0x7 << 8) | (0x7 << 12) |
 			(0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28),
 			(0x3 << 8) | (0x3 << 12) |
 			(0x3 << 16) | (0x3 << 20) | (0x3 << 24) | (0x3 << 28));
-		clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2],
+		clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[2],
 			0x77777777, _SELPH_DQS_BITS(0x2, 0x0));
-		clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3],
+		clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[3],
 			0x77777777, _SELPH_DQS_BITS(0x2, 0x0));
 	}
 
-	clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry,
+	clrsetbits32(&ch[0].ao.shu[0].dqsg_retry,
 		(0x1 << 2) | (0xf << 8), (0x1 << 2) | (0x4 << 8));
-	clrsetbits_le32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x3 << 20);
-	clrsetbits_le32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13),
+	clrsetbits32(&ch[0].phy.b[0].dq[5], 0x7 << 20, 0x3 << 20);
+	clrsetbits32(&ch[0].phy.b[0].dq[7], (0x3 << 4) | (0x1 << 7) | (0x1 << 13),
 		(0x1 << 4) | (0x1 << 7) | (0x1 << 13));
-	clrsetbits_le32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x3 << 20);
-	clrsetbits_le32(&ch[0].phy.b[1].dq[7],
+	clrsetbits32(&ch[0].phy.b[1].dq[5], 0x7 << 20, 0x3 << 20);
+	clrsetbits32(&ch[0].phy.b[1].dq[7],
 		(0x1 << 7) | (0x1 << 13), (0x1 << 7) | (0x1 << 13));
 
 	for (size_t r = 0; r < 2; r++) {
 		for (size_t b = 0; b < 2; b++)
-			clrsetbits_le32(&ch[0].phy.shu[0].rk[r].b[b].dq[7],
+			clrsetbits32(&ch[0].phy.shu[0].rk[r].b[b].dq[7],
 				(0x3f << 8) | (0x3f << 16), (0x14 << 8) | (0x14 << 16));
 	}
 }
 
 static void dramc_setting_DDR3600(void)
 {
-	clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_3600);
-	clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_3600);
+	clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_3600);
+	clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_3600);
 }
 
 static void dramc_setting(const struct sdram_params *params, u8 freq_group,
@@ -990,158 +990,158 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group,
 	dramc_set_broadcast(DRAMC_BROADCAST_OFF);
 
 	for (chn = 0; chn < CHANNEL_MAX; chn++)
-		setbits_le32(&ch[chn].phy.ckmux_sel, (0x1 << 0) | (0x1 << 1));
+		setbits32(&ch[chn].phy.ckmux_sel, (0x1 << 0) | (0x1 << 1));
 
 	dramc_set_broadcast(DRAMC_BROADCAST_ON);
 
-	setbits_le32(&ch[0].phy.misc_cg_ctrl0, 0x1 << 0);
+	setbits32(&ch[0].phy.misc_cg_ctrl0, 0x1 << 0);
 
 	/* 26M */
-	clrbits_le32(&ch[0].phy.misc_cg_ctrl0, 0x3 << 4);
-	clrbits_le32(&ch[0].phy.misc_ctrl0, 0x1 << 17);
+	clrbits32(&ch[0].phy.misc_cg_ctrl0, 0x3 << 4);
+	clrbits32(&ch[0].phy.misc_ctrl0, 0x1 << 17);
 
-	clrbits_le32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0);
+	clrbits32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0);
 	write32(&ch[0].phy.misc_spm_ctrl2, 0x0);
 	write32(&ch[0].phy.misc_spm_ctrl0, 0x0);
 	write32(&ch[0].phy.misc_cg_ctrl2, 0x6003bf);
 	write32(&ch[0].phy.misc_cg_ctrl4, 0x333f3f00);
-	setbits_le32(&ch[0].phy.shu[0].pll[1], (0x1 << 4) | (0x7 << 1));
-	clrsetbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x3f << 0, 0x10 << 0);
-	clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x0f << 0);
+	setbits32(&ch[0].phy.shu[0].pll[1], (0x1 << 4) | (0x7 << 1));
+	clrsetbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x3f << 0, 0x10 << 0);
+	clrbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x0f << 0);
 
 	for (size_t b = 0; b <= 2; b += 2)
-		clrsetbits_le32(&ch[0].phy.shu[0].pll[4 + b],
+		clrsetbits32(&ch[0].phy.shu[0].pll[4 + b],
 			 (0x3 << 18) | (0x3 << 24) | (0x3 << 26),
 			 (0x2 << 18) | (0x1 << 24) | (0x1 << 26));
 
-	clrbits_le32(&ch[0].phy.shu[0].pll[14], 0x1 << 1);
-	clrbits_le32(&ch[0].phy.shu[0].pll20, 0x1 << 1);
-	clrbits_le32(&ch[0].phy.ca_cmd[2], (0x3 << 16) | (0x3 << 20));
+	clrbits32(&ch[0].phy.shu[0].pll[14], 0x1 << 1);
+	clrbits32(&ch[0].phy.shu[0].pll20, 0x1 << 1);
+	clrbits32(&ch[0].phy.ca_cmd[2], (0x3 << 16) | (0x3 << 20));
 	for (size_t b = 0; b < 2; b++)
-		clrbits_le32(&ch[0].phy.b[b].dq[2], (0x3 << 16) | (0x3 << 20));
+		clrbits32(&ch[0].phy.b[b].dq[2], (0x3 << 16) | (0x3 << 20));
 	for (size_t b = 0; b < 2; b++)
-		clrsetbits_le32(&ch[0].phy.b[b].dq[9], 0x7 << 28, 0x1 << 28);
-	clrbits_le32(&ch[0].phy.ca_cmd[10], 0x7 << 28);
+		clrsetbits32(&ch[0].phy.b[b].dq[9], 0x7 << 28, 0x1 << 28);
+	clrbits32(&ch[0].phy.ca_cmd[10], 0x7 << 28);
 
-	setbits_le32(&ch[0].phy.b0_rxdvs[0], 0x1 << 28);
-	setbits_le32(&ch[0].phy.b1_rxdvs[0], 0x1 << 28);
-	setbits_le32(&ch[0].phy.b0_rxdvs[0], 0x1 << 9);
-	setbits_le32(&ch[0].phy.b1_rxdvs[0], 0x1 << 9);
+	setbits32(&ch[0].phy.b0_rxdvs[0], 0x1 << 28);
+	setbits32(&ch[0].phy.b1_rxdvs[0], 0x1 << 28);
+	setbits32(&ch[0].phy.b0_rxdvs[0], 0x1 << 9);
+	setbits32(&ch[0].phy.b1_rxdvs[0], 0x1 << 9);
 
 	for (size_t b = 0; b < 2; b++) {
 		for (size_t r = 0; r < 2; r++)
-			setbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2], 0x1 << 29);
-		clrsetbits_le32(&ch[0].phy.shu[0].b[b].dq[5], 0x7 << 20, 0x3 << 20);
+			setbits32(&ch[0].phy.r[r].b[b].rxdvs[2], 0x1 << 29);
+		clrsetbits32(&ch[0].phy.shu[0].b[b].dq[5], 0x7 << 20, 0x3 << 20);
 
 		for (size_t r = 0; r < 2; r++) {
-			clrsetbits_le32(&ch[0].phy.r[r].b[b].rxdvs[1],
+			clrsetbits32(&ch[0].phy.r[r].b[b].rxdvs[1],
 				(0xffff << 0) | (0xffff << 16), (0x2 << 0) | (0x2 << 16));
-			clrsetbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2],
+			clrsetbits32(&ch[0].phy.r[r].b[b].rxdvs[2],
 				(0x1 << 23) | (0x1 << 28) | (0x3 << 30),
 				(0x1 << 23) | (0x1 << 28) | (0x2 << 30));
 		}
 	}
 
-	clrbits_le32(&ch[0].phy.b0_rxdvs[0], 0x1 << 28);
-	clrbits_le32(&ch[0].phy.b1_rxdvs[0], 0x1 << 28);
+	clrbits32(&ch[0].phy.b0_rxdvs[0], 0x1 << 28);
+	clrbits32(&ch[0].phy.b1_rxdvs[0], 0x1 << 28);
 
 	for (size_t b = 0; b < 2; b++) {
-		setbits_le32(&ch[0].phy.b[b].dq[9], 0x1 << 0);
+		setbits32(&ch[0].phy.b[b].dq[9], 0x1 << 0);
 		for (size_t r = 0; r < 2; r++)
-			clrsetbits_le32(&ch[0].phy.shu[0].rk[r].b[b].dq[7],
+			clrsetbits32(&ch[0].phy.shu[0].rk[r].b[b].dq[7],
 				(0x3f << 8) | (0x3f << 16), (0x1f << 8) | (0x1f << 16));
 
-		clrsetbits_le32(&ch[0].phy.b[b].dq[4],
+		clrsetbits32(&ch[0].phy.b[b].dq[4],
 			(0x7f << 0) | (0x7f << 8), (0x10 << 0) | (0x10 << 8));
-		clrsetbits_le32(&ch[0].phy.b[b].dq[5],
+		clrsetbits32(&ch[0].phy.b[b].dq[5],
 			(0xff << 0) | (0x3f << 8) | (0x1 << 16) | (0xf << 20) | (0x1 << 24),
 			(0x10 << 0) | (0xe << 8) | (0x1 << 16) | (0x1 << 20) | (0x0 << 24));
-		clrsetbits_le32(&ch[0].phy.b[b].dq[6],
+		clrsetbits32(&ch[0].phy.b[b].dq[6],
 			(0x1 << 4) | (0x1 << 7) | (0x1 << 12) | (0x3 << 14) |
 			(0xf << 16) | (0x1 << 24),
 			(0x0 << 4) | (0x1 << 7) | (0x1 << 12) | (0x0 << 14) |
 			(0x3 << 16) | (0x1 << 24));
-		clrsetbits_le32(&ch[0].phy.b[b].dq[5],
+		clrsetbits32(&ch[0].phy.b[b].dq[5],
 			(0xff << 0) | (0x1 << 25), (0x0 << 0) | (0x1 << 25));
 	}
 
-	setbits_le32(&ch[0].phy.ca_cmd[3], (0x3 << 2) | (0x1 << 7));
-	clrsetbits_le32(&ch[0].phy.ca_cmd[6], (0x1 << 6) | (0x3 << 14) | (0x1 << 16),
+	setbits32(&ch[0].phy.ca_cmd[3], (0x3 << 2) | (0x1 << 7));
+	clrsetbits32(&ch[0].phy.ca_cmd[6], (0x1 << 6) | (0x3 << 14) | (0x1 << 16),
 		(0x0 << 6) | (0x0 << 14) | (0x0 << 16));
 
-	clrbits_le32(&ch[0].phy.pll3, 0x1 < 0);
-	setbits_le32(&ch[0].phy.b[0].dq[3], 0x1 << 3);
-	setbits_le32(&ch[0].phy.b[1].dq[3], 0x1 << 3);
+	clrbits32(&ch[0].phy.pll3, 0x1 < 0);
+	setbits32(&ch[0].phy.b[0].dq[3], 0x1 << 3);
+	setbits32(&ch[0].phy.b[1].dq[3], 0x1 << 3);
 
 	udelay(1);
-	clrsetbits_le32(&ch[0].phy.shu[0].pll[8],
+	clrsetbits32(&ch[0].phy.shu[0].pll[8],
 		(0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18));
 
 	udelay(1);
-	clrbits_le32(&ch[0].phy.shu[0].pll[9],
+	clrbits32(&ch[0].phy.shu[0].pll[9],
 		 (0x3 << 8) | (0x1 << 12) | (0x3 << 14) | (0x1 << 16));
-	clrbits_le32(&ch[0].phy.shu[0].pll[11],
+	clrbits32(&ch[0].phy.shu[0].pll[11],
 		 (0x3 << 8) | (0x1 << 12) | (0x3 << 14) | (0x1 << 16));
 	udelay(1);
 
-	clrsetbits_le32(&ch[0].phy.shu[0].pll[10],
+	clrsetbits32(&ch[0].phy.shu[0].pll[10],
 		(0x7 << 0) | (0x3 << 18), (0x0 << 0) | (0x1 << 18));
 	udelay(1);
 
 	/* PLL EN */
 	/* MID FINE_TUNE Init 1 */
-	clrsetbits_le32(&ch[0].phy.pll4, (0x3 << 18) | (0x1 << 21), 0x3 << 18);
+	clrsetbits32(&ch[0].phy.pll4, (0x3 << 18) | (0x1 << 21), 0x3 << 18);
 
 	udelay(1);
-	clrsetbits_le32(&ch[0].phy.shu[0].pll[0], 0xffff << 0, 0x3 << 0);
+	clrsetbits32(&ch[0].phy.shu[0].pll[0], 0xffff << 0, 0x3 << 0);
 
 	udelay(1);
-	setbits_le32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 21);
+	setbits32(&ch[0].phy.ca_dll_fine_tune[1], 0x1 << 21);
 
 	for (size_t b = 0; b < 2; b++)
-		setbits_le32(&ch[0].phy.b[b].dq[3], (0x3 << 1) | (0x1 << 10));
-	setbits_le32(&ch[0].phy.shu[0].ca_dll[0], 0x1 << 0);
+		setbits32(&ch[0].phy.b[b].dq[3], (0x3 << 1) | (0x1 << 10));
+	setbits32(&ch[0].phy.shu[0].ca_dll[0], 0x1 << 0);
 
 	for (size_t b = 0; b < 2; b++)
-		clrsetbits_le32(&ch[0].phy.shu[0].b[b].dll[0],
+		clrsetbits32(&ch[0].phy.shu[0].b[b].dll[0],
 			(0x1 << 4) | (0x3 << 9) | (0xf << 12) |
 			(0xf << 16) | (0xf << 20) | (0x1 << 30),
 			(0x0 << 4) | (0x3 << 9) | (0x8 << 12) |
 			(0x7 << 16) | (0x7 << 20) | (0x1 << 30));
 
-	clrbits_le32(&ch[0].phy.shu[0].ca_cmd[5], 0x3f << 0);
-	clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[0],
+	clrbits32(&ch[0].phy.shu[0].ca_cmd[5], 0x3f << 0);
+	clrsetbits32(&ch[0].phy.shu[0].ca_cmd[0],
 		(0x1 << 4) | (0x7 << 12) | (0x1 << 20),
 		(0x1 << 4) | (0x4 << 12) | (0x1 << 20));
 
 	dramc_set_broadcast(DRAMC_BROADCAST_OFF);
-	clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[6], 0xffff << 6, 0x3 << 6);
-	clrsetbits_le32(&ch[1].phy.shu[0].ca_cmd[6], 0xffff << 6, 0x1 << 6);
+	clrsetbits32(&ch[0].phy.shu[0].ca_cmd[6], 0xffff << 6, 0x3 << 6);
+	clrsetbits32(&ch[1].phy.shu[0].ca_cmd[6], 0xffff << 6, 0x1 << 6);
 	dramc_set_broadcast(DRAMC_BROADCAST_ON);
 
 	for (size_t b = 0; b < 2; b++)
-		clrsetbits_le32(&ch[0].phy.shu[0].b[b].dq[6], 0xffff << 6, 0x1 << 6);
+		clrsetbits32(&ch[0].phy.shu[0].b[b].dq[6], 0xffff << 6, 0x1 << 6);
 
 	dramc_set_broadcast(DRAMC_BROADCAST_OFF);
 	for (chn = 0; chn < CHANNEL_MAX; chn++)
-		clrsetbits_le32(&ch[chn].phy.misc_shu_opt,
+		clrsetbits32(&ch[chn].phy.misc_shu_opt,
 			(0x1 << 0) | (0x3 << 2) | (0x1 << 8) |
 			(0x3 << 10) | (0x1 << 16) | (0x3 << 18),
 			(0x1 << 0) | (0x2 << 2) | (0x1 << 8) |
 			(0x2 << 10) | (0x1 << 16) | ((0x1 + chn) << 18));
 
 	udelay(9);
-	clrsetbits_le32(&ch[0].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 2);
-	clrsetbits_le32(&ch[1].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 0);
+	clrsetbits32(&ch[0].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 2);
+	clrsetbits32(&ch[1].phy.shu[0].ca_dll[1], (0x1 << 0) | (0x1 << 2), 0x1 << 0);
 	dramc_set_broadcast(DRAMC_BROADCAST_ON);
 
 	for (size_t b = 0; b < 2; b++)
-		clrsetbits_le32(&ch[0].phy.shu[0].b[b].dll[1],
+		clrsetbits32(&ch[0].phy.shu[0].b[b].dll[1],
 			(0x1 << 0) | (0x1 << 2), (0x1 << 0) | (0x0 << 2));
 	udelay(1);
 
-	clrbits_le32(&ch[0].phy.pll2, 0x1 << 31);
-	clrsetbits_le32(&ch[0].phy.misc_cg_ctrl0, 0xffffffff, 0xf);
+	clrbits32(&ch[0].phy.pll2, 0x1 << 31);
+	clrsetbits32(&ch[0].phy.misc_cg_ctrl0, 0xffffffff, 0xf);
 	udelay(1);
 
 	dramc_set_broadcast(DRAMC_BROADCAST_OFF);
@@ -1150,241 +1150,241 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group,
 		ddr_phy_pll_setting(chn, freq_group);
 
 	dramc_set_broadcast(DRAMC_BROADCAST_ON);
-	setbits_le32(&ch[0].ao.drsctrl, 0x1 << 29);
+	setbits32(&ch[0].ao.drsctrl, 0x1 << 29);
 
 	/* Set Run time MRR CKE fix to 1 in tMRRI old mode
 	 * to avoid no ACK from precharge all */
-	setbits_le32(&ch[0].ao.ckectrl, 0x1 << 27);
-	clrsetbits_le32(&ch[0].ao.dramctrl,
+	setbits32(&ch[0].ao.ckectrl, 0x1 << 27);
+	clrsetbits32(&ch[0].ao.dramctrl,
 		(0x1 << 15) | (0x1 << 17) | (0x1 << 23),
 		(0x0 << 15) | (0x1 << 17) | (0x1 << 23));
-	setbits_le32(&ch[0].ao.spcmdctrl, (0x1 << 1) | (0x1 << 8) | (0x1 << 9) | (0x1 << 10));
-	setbits_le32(&ch[0].phy.b[0].dq[9], 0x1 << 4);
-	setbits_le32(&ch[0].phy.b[1].dq[9], 0x1 << 4);
+	setbits32(&ch[0].ao.spcmdctrl, (0x1 << 1) | (0x1 << 8) | (0x1 << 9) | (0x1 << 10));
+	setbits32(&ch[0].phy.b[0].dq[9], 0x1 << 4);
+	setbits32(&ch[0].phy.b[1].dq[9], 0x1 << 4);
 
-	clrsetbits_le32(&ch[0].ao.shu[0].rk[1].dqsien,
+	clrsetbits32(&ch[0].ao.shu[0].rk[1].dqsien,
 		(0x7f << 0) | (0x7f << 8) | (0x7f << 16) | (0x7f << 24),
 		(0xf << 0) | (0xf << 8) | (0xf << 16) | (0xf << 24));
-	clrsetbits_le32(&ch[0].ao.stbcal1,
+	clrsetbits32(&ch[0].ao.stbcal1,
 		(0x1 << 4) | (0x1 << 8) | (0x1 << 12), (0x1 << 4) | (0x1 << 8));
-	clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry,
+	clrsetbits32(&ch[0].ao.shu[0].dqsg_retry,
 		(0x1 << 3) | (0xf << 8) | (0x1 << 21) | (0x1 << 31),
 		(0x1 << 3) | (0x6 << 8) | (0x1 << 21) | (0x1 << 31));
 
 	for (size_t i = 0; i < 4; i++) {
-		clrsetbits_le32(&ch[0].ao.shu[0].drving[i],
+		clrsetbits32(&ch[0].ao.shu[0].drving[i],
 			(0x1f << 0) | (0x1f << 5) | (0x1f << 10) |
 			(0x1f << 15) | (0x1f << 20) | (0x1f << 25),
 			(0xa << 0) | (0xa << 5) | (0xa << 10) |
 			(0xa << 15) | (0xa << 20) | (0xa << 25));
 	}
 
-	clrsetbits_le32(&ch[0].ao.shuctrl2,
+	clrsetbits32(&ch[0].ao.shuctrl2,
 		(0x3f << 0) | (0x1 << 12) | (0x1 << 14) |
 		(0x1 << 15) | (0xff << 16) | (0x1 << 24),
 		(0xa << 0) | (0x1 << 12) | (0x1 << 14) |
 		(0x1 << 15) | (0x1 << 16) | (0x0 << 24));
-	setbits_le32(&ch[0].ao.dvfsdll, 0x1 << 0);
-	setbits_le32(&ch[0].ao.ddrconf0,
+	setbits32(&ch[0].ao.dvfsdll, 0x1 << 0);
+	setbits32(&ch[0].ao.ddrconf0,
 		(0x1 << 12) | (0x1 << 15) | (0x1 << 20) | (0x1 << 26));
-	setbits_le32(&ch[0].ao.stbcal2, (0x1 << 4) | (0x7 << 28));
-	clrbits_le32(&ch[0].ao.stbcal2, 0x1 << 29);
-	setbits_le32(&ch[0].ao.clkar, 0x1 << 19);
+	setbits32(&ch[0].ao.stbcal2, (0x1 << 4) | (0x7 << 28));
+	clrbits32(&ch[0].ao.stbcal2, 0x1 << 29);
+	setbits32(&ch[0].ao.clkar, 0x1 << 19);
 
 	for (size_t b = 0; b < 2; b++)
-		clrsetbits_le32(&ch[0].phy.b[b].dq[9], 0x7 << 20, 0x1 << 20);
-	clrsetbits_le32(&ch[0].phy.ca_cmd[10], 0x7 << 20, 0x0 << 20);
-	setbits_le32(&ch[0].phy.misc_ctrl0,
+		clrsetbits32(&ch[0].phy.b[b].dq[9], 0x7 << 20, 0x1 << 20);
+	clrsetbits32(&ch[0].phy.ca_cmd[10], 0x7 << 20, 0x0 << 20);
+	setbits32(&ch[0].phy.misc_ctrl0,
 		(0xf << 0) | (0x1 << 9) | (0x1 << 24) | (0x1 << 31));
 
-	setbits_le32(&ch[0].phy.misc_ctrl1,
+	setbits32(&ch[0].phy.misc_ctrl1,
 		 (0x1 << 2) | (0x1 << 3) | (0x1 << 15) | (0x1 << 24));
-	clrsetbits_le32(&ch[0].phy.b0_rxdvs[0], 0x1 << 24, 0x1 << 24);
-	clrsetbits_le32(&ch[0].phy.b1_rxdvs[0], 0x1 << 24, 0x1 << 24);
-	clrsetbits_le32(&ch[0].phy.ca_rxdvs0, 0x1 << 24, 0x0 << 24);
-	clrbits_le32(&ch[0].phy.ca_cmd[7], (0x1 << 4) | (0x1 << 6));
-	clrbits_le32(&ch[0].phy.b[0].dq[7], 0x1 << 6);
-	clrbits_le32(&ch[0].phy.b[1].dq[7], 0x1 << 6);
-
-	clrsetbits_le32(&ch[0].ao.shu[0].conf[0],
+	clrsetbits32(&ch[0].phy.b0_rxdvs[0], 0x1 << 24, 0x1 << 24);
+	clrsetbits32(&ch[0].phy.b1_rxdvs[0], 0x1 << 24, 0x1 << 24);
+	clrsetbits32(&ch[0].phy.ca_rxdvs0, 0x1 << 24, 0x0 << 24);
+	clrbits32(&ch[0].phy.ca_cmd[7], (0x1 << 4) | (0x1 << 6));
+	clrbits32(&ch[0].phy.b[0].dq[7], 0x1 << 6);
+	clrbits32(&ch[0].phy.b[1].dq[7], 0x1 << 6);
+
+	clrsetbits32(&ch[0].ao.shu[0].conf[0],
 		(0x3f << 0) | (0x1 << 7) | (0xf << 12) | (0x1 << 24) |
 		(0x1 << 29) | (0x3 << 30),
 		(0x3f << 0) | (0x1 << 7) | (0x1 << 12) | (0x1 << 24) |
 		(0x1 << 29) | (0x2 << 30));
-	clrsetbits_le32(&ch[0].ao.shu[0].odtctrl,
+	clrsetbits32(&ch[0].ao.shu[0].odtctrl,
 		(0x1 << 0) | (0x1 << 1) | (0x7f << 16) | (0x1 << 30) | (0x1 << 31),
 		(0x1 << 0) | (0x1 << 1) | (0x1 << 16) | (0x1 << 30) | (0x1 << 31));
-	setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15);
-	setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15);
+	setbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 15);
+	setbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 15);
 
-	clrsetbits_le32(&ch[0].ao.refctrl0, 0xf << 24, 0x5 << 24);
-	clrbits_le32(&ch[0].ao.shu[0].selph_ca1,
+	clrsetbits32(&ch[0].ao.refctrl0, 0xf << 24, 0x5 << 24);
+	clrbits32(&ch[0].ao.shu[0].selph_ca1,
 		 (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) |
 		 (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28));
-	clrsetbits_le32(&ch[0].ao.shu[0].selph_ca2,
+	clrsetbits32(&ch[0].ao.shu[0].selph_ca2,
 		 (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 16) | (0x7 << 24),
 		 (0x0 << 0) | (0x0 << 4) | (0x0 << 8) | (0x7 << 16) | (0x0 << 24));
-	clrbits_le32(&ch[0].ao.shu[0].selph_ca3,
+	clrbits32(&ch[0].ao.shu[0].selph_ca3,
 		 (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) |
 		 (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28));
-	clrbits_le32(&ch[0].ao.shu[0].selph_ca4,
+	clrbits32(&ch[0].ao.shu[0].selph_ca4,
 		 (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12)  |
 		 (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28));
-	clrbits_le32(&ch[0].ao.shu[0].selph_ca5, 0x7 << 8);
-	clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0);
-	clrsetbits_le32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1);
+	clrbits32(&ch[0].ao.shu[0].selph_ca5, 0x7 << 8);
+	clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0);
+	clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1);
 
 	for (size_t rank = 0; rank < 2; rank++) {
-		clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[0],
+		clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[0],
 			0x77777777, _SELPH_DQS_BITS(0x3, 0x3));
-		clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[1],
+		clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[1],
 			0x77777777, _SELPH_DQS_BITS(0x3, 0x3));
-		clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2],
+		clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[2],
 			0x77777777, _SELPH_DQS_BITS(0x6, 0x2));
-		clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3],
+		clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[3],
 			0x77777777, _SELPH_DQS_BITS(0x6, 0x2));
 	}
 
 	for (int b = 0; b < 2; b++) {
-		clrsetbits_le32(&ch[0].phy.shu[0].rk[0].b[b].dq[7],
+		clrsetbits32(&ch[0].phy.shu[0].rk[0].b[b].dq[7],
 			(0x3f << 8) | (0x3f << 16), (0x1a << 8) | (0x1a << 16));
-		clrsetbits_le32(&ch[0].phy.shu[0].rk[1].b[b].dq[7],
+		clrsetbits32(&ch[0].phy.shu[0].rk[1].b[b].dq[7],
 			(0x3f << 8) | (0x3f << 16), (0x14 << 8) | (0x14 << 16));
 	}
 	udelay(1);
 
 	for (size_t b = 0; b < 2; b++) {
-		setbits_le32(&ch[0].phy.b[b].dq[9], 0x1 << 5);
-		clrsetbits_le32(&ch[0].phy.b[b].dq[6], 0x3 << 14, 0x1 << 14);
+		setbits32(&ch[0].phy.b[b].dq[9], 0x1 << 5);
+		clrsetbits32(&ch[0].phy.b[b].dq[6], 0x3 << 14, 0x1 << 14);
 	}
-	setbits_le32(&ch[0].ao.stbcal, 0x1 << 31);
-	clrsetbits_le32(&ch[0].ao.srefctrl, (0xf << 24) | (0x1 << 30), 0x8 << 24);
-	clrsetbits_le32(&ch[0].ao.shu[0].ckectrl,
+	setbits32(&ch[0].ao.stbcal, 0x1 << 31);
+	clrsetbits32(&ch[0].ao.srefctrl, (0xf << 24) | (0x1 << 30), 0x8 << 24);
+	clrsetbits32(&ch[0].ao.shu[0].ckectrl,
 		(0x3 << 24) | (0x3 << 28), (0x3 << 24) | (0x3 << 28));
-	setbits_le32(&ch[0].ao.shu[0].pipe, (0x1 << 30) | (0x1 << 31));
-	setbits_le32(&ch[0].ao.ckectrl, (0x1 << 13) | (0x1 << 31));
-	setbits_le32(&ch[0].ao.rkcfg, 0x1 << 2);
-	clrsetbits_le32(&ch[0].ao.shu[0].conf[2],
+	setbits32(&ch[0].ao.shu[0].pipe, (0x1 << 30) | (0x1 << 31));
+	setbits32(&ch[0].ao.ckectrl, (0x1 << 13) | (0x1 << 31));
+	setbits32(&ch[0].ao.rkcfg, 0x1 << 2);
+	clrsetbits32(&ch[0].ao.shu[0].conf[2],
 		(0x7 << 16) | (0x1 << 28), (0x7 << 16) | (0x1 << 28));
-	clrsetbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 26, 0x1 << 26);
-	clrsetbits_le32(&ch[0].ao.shuctrl1, 0xff << 0, 0x40 << 0);
+	clrsetbits32(&ch[0].ao.spcmdctrl, 0x1 << 26, 0x1 << 26);
+	clrsetbits32(&ch[0].ao.shuctrl1, 0xff << 0, 0x40 << 0);
 
-	setbits_le32(&ch[0].ao.shuctrl, 0x1 << 16);
-	clrbits_le32(&ch[0].ao.refctrl1, (0x1 << 1) | (0x1 << 2) | (0x1 << 3) | (0x1 << 6));
-	clrsetbits_le32(&ch[0].ao.refratre_filter, (0x1 << 15) | (0x1 << 23),
+	setbits32(&ch[0].ao.shuctrl, 0x1 << 16);
+	clrbits32(&ch[0].ao.refctrl1, (0x1 << 1) | (0x1 << 2) | (0x1 << 3) | (0x1 << 6));
+	clrsetbits32(&ch[0].ao.refratre_filter, (0x1 << 15) | (0x1 << 23),
 		(0x1 << 15) | (0x0 << 23));
-	clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 9);
-	setbits_le32(&ch[0].ao.misctl0, (0x1 << 19) | (0x1 << 24) | (0x1 << 31));
-	setbits_le32(&ch[0].ao.perfctl0,
+	clrbits32(&ch[0].ao.dramctrl, 0x1 << 9);
+	setbits32(&ch[0].ao.misctl0, (0x1 << 19) | (0x1 << 24) | (0x1 << 31));
+	setbits32(&ch[0].ao.perfctl0,
 		(0x1 << 0) | (0x1 << 1) | (0x1 << 4) | (0x1 << 8) |
 		(0x1 << 9) | (0x1 << 10) | (0x1 << 11) | (0x1 << 14) | (0x1 << 17));
-	clrsetbits_le32(&ch[0].ao.arbctl, 0xff << 0, 0x80 << 0);
-	clrsetbits_le32(&ch[0].ao.padctrl, (0x3 << 0) | (0x1 << 3), (0x1 << 0) | (0x1 << 3));
-	setbits_le32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 8);
-	setbits_le32(&ch[0].ao.clkctrl, 0x1 << 29);
-	clrsetbits_le32(&ch[0].ao.refctrl0, (0x1 << 0) | (0x7 << 12), (0x1 << 0) | (0x4 << 12));
-	clrsetbits_le32(&ch[0].ao.shu[0].rankctl, (0xf << 20) | (0xf << 24) | (0xf << 28),
+	clrsetbits32(&ch[0].ao.arbctl, 0xff << 0, 0x80 << 0);
+	clrsetbits32(&ch[0].ao.padctrl, (0x3 << 0) | (0x1 << 3), (0x1 << 0) | (0x1 << 3));
+	setbits32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 8);
+	setbits32(&ch[0].ao.clkctrl, 0x1 << 29);
+	clrsetbits32(&ch[0].ao.refctrl0, (0x1 << 0) | (0x7 << 12), (0x1 << 0) | (0x4 << 12));
+	clrsetbits32(&ch[0].ao.shu[0].rankctl, (0xf << 20) | (0xf << 24) | (0xf << 28),
 		(0x4 << 20) | (0x4 << 24) | (0x6 << 28));
 	udelay(2);
 
-	clrsetbits_le32(&ch[0].ao.shu[0].rk[0].dqsien,
+	clrsetbits32(&ch[0].ao.shu[0].rk[0].dqsien,
 		(0x7f << 0) | (0x7f << 8), (0x19 << 0) | (0x19 << 8));
-	clrsetbits_le32(&ch[0].ao.shu[0].rk[1].dqsien,
+	clrsetbits32(&ch[0].ao.shu[0].rk[1].dqsien,
 		(0x7f << 0) | (0x7f << 8) | (0x7f << 16) | (0x7f << 24),
 		(0x1b << 0) | (0x1b << 8) | (0x0 << 16) | (0x0 << 24));
 
-	setbits_le32(&ch[0].ao.dramctrl, 0x1 << 19);
-	clrsetbits_le32(&ch[0].ao.zqcs, 0xff << 0, 0x56 << 0);
+	setbits32(&ch[0].ao.dramctrl, 0x1 << 19);
+	clrsetbits32(&ch[0].ao.zqcs, 0xff << 0, 0x56 << 0);
 	udelay(1);
 
-	clrsetbits_le32(&ch[0].ao.shu[0].conf[3], 0x1ff << 16, 0xff << 16);
-	setbits_le32(&ch[0].ao.refctrl0, 0x1 << 30);
-	setbits_le32(&ch[0].ao.srefctrl, 0x1 << 30);
-	setbits_le32(&ch[0].ao.mpc_option, 0x1 << 17);
-	setbits_le32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 30);
-	setbits_le32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 0);
-	clrsetbits_le32(&ch[0].ao.eyescan, (0x1 << 1) | (0xf << 16), (0x0 << 1) | (0x1 << 16));
-	setbits_le32(&ch[0].ao.stbcal1, (0x1 << 10) | (0x1 << 11));
-	clrsetbits_le32(&ch[0].ao.test2_1, 0xfffffff << 4, 0x10000 << 4);
-	clrsetbits_le32(&ch[0].ao.test2_2, 0xfffffff << 4, 0x400 << 4);
-	clrsetbits_le32(&ch[0].ao.test2_3,
+	clrsetbits32(&ch[0].ao.shu[0].conf[3], 0x1ff << 16, 0xff << 16);
+	setbits32(&ch[0].ao.refctrl0, 0x1 << 30);
+	setbits32(&ch[0].ao.srefctrl, 0x1 << 30);
+	setbits32(&ch[0].ao.mpc_option, 0x1 << 17);
+	setbits32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 30);
+	setbits32(&ch[0].ao.dramc_pd_ctrl, 0x1 << 0);
+	clrsetbits32(&ch[0].ao.eyescan, (0x1 << 1) | (0xf << 16), (0x0 << 1) | (0x1 << 16));
+	setbits32(&ch[0].ao.stbcal1, (0x1 << 10) | (0x1 << 11));
+	clrsetbits32(&ch[0].ao.test2_1, 0xfffffff << 4, 0x10000 << 4);
+	clrsetbits32(&ch[0].ao.test2_2, 0xfffffff << 4, 0x400 << 4);
+	clrsetbits32(&ch[0].ao.test2_3,
 		(0x1 << 7) | (0x7 << 8) | (0x1 << 28),
 		(0x1 << 7) | (0x4 << 8) | (0x1 << 28));
-	clrbits_le32(&ch[0].ao.rstmask, 0x1 << 29);
-	clrbits_le32(&ch[0].ao.rstmask, 0x1 << 30);
+	clrbits32(&ch[0].ao.rstmask, 0x1 << 29);
+	clrbits32(&ch[0].ao.rstmask, 0x1 << 30);
 
 	udelay(1);
-	clrsetbits_le32(&ch[0].ao.hw_mrr_fun, (0xf << 0) | (0xf << 4), (0x8 << 0) | (0x6 << 4));
+	clrsetbits32(&ch[0].ao.hw_mrr_fun, (0xf << 0) | (0xf << 4), (0x8 << 0) | (0x6 << 4));
 
-	clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 0);
-	clrsetbits_le32(&ch[0].ao.perfctl0,
+	clrbits32(&ch[0].ao.dramctrl, 0x1 << 0);
+	clrsetbits32(&ch[0].ao.perfctl0,
 		(0x1 << 18) | (0x1 << 19), (0x0 << 18) | (0x1 << 19));
-	setbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 28);
-	clrbits_le32(&ch[0].ao.rstmask, 0x1 << 28);
-	setbits_le32(&ch[0].ao.rkcfg, 0x1 << 11);
-	setbits_le32(&ch[0].ao.mpc_option, 0x1 << 17);
-	setbits_le32(&ch[0].ao.eyescan, 0x1 << 2);
-	setbits_le32(&ch[0].ao.shu[0].wodt, 0x1 << 29);
-	setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 7);
-	setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 7);
-	clrsetbits_le32(&ch[0].ao.shu[0].rankctl, 0xf << 20, 0x4 << 20);
+	setbits32(&ch[0].ao.spcmdctrl, 0x1 << 28);
+	clrbits32(&ch[0].ao.rstmask, 0x1 << 28);
+	setbits32(&ch[0].ao.rkcfg, 0x1 << 11);
+	setbits32(&ch[0].ao.mpc_option, 0x1 << 17);
+	setbits32(&ch[0].ao.eyescan, 0x1 << 2);
+	setbits32(&ch[0].ao.shu[0].wodt, 0x1 << 29);
+	setbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 7);
+	setbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 7);
+	clrsetbits32(&ch[0].ao.shu[0].rankctl, 0xf << 20, 0x4 << 20);
 
 	for (size_t r = 0; r < 2; r++) {
-		clrsetbits_le32(&ch[0].ao.shu[0].rk[r].selph_dq[0],
+		clrsetbits32(&ch[0].ao.shu[0].rk[r].selph_dq[0],
 			(0x7 << 0) | (0x7 << 4), (0x2 << 0) | (0x2 << 4));
-		clrsetbits_le32(&ch[0].ao.shu[0].rk[r].selph_dq[1],
+		clrsetbits32(&ch[0].ao.shu[0].rk[r].selph_dq[1],
 			(0x7 << 0) | (0x7 << 4), (0x2 << 0) | (0x2 << 4));
 	}
 	udelay(5);
 
-	clrsetbits_le32(&ch[0].ao.stbcal1, 0xffff << 16, 0x3 << 16);
-	clrsetbits_le32(&ch[0].ao.stbcal1, 0xffff << 16, 0x1 << 16);
-	clrsetbits_le32(&ch[0].ao.stbcal,
+	clrsetbits32(&ch[0].ao.stbcal1, 0xffff << 16, 0x3 << 16);
+	clrsetbits32(&ch[0].ao.stbcal1, 0xffff << 16, 0x1 << 16);
+	clrsetbits32(&ch[0].ao.stbcal,
 		(0x1 << 0) | (0x1 << 22) | (0x1 << 24) | (0x1 << 26) | (0x1 << 27),
 		(0x1 << 0) | (0x0 << 22) | (0x0 << 24) | (0x1 << 26) | (0x1 << 27));
-	setbits_le32(&ch[0].ao.stbcal1, 0x1 << 6);
-	clrsetbits_le32(&ch[0].ao.shu[0].dqsg,
+	setbits32(&ch[0].ao.stbcal1, 0x1 << 6);
+	clrsetbits32(&ch[0].ao.shu[0].dqsg,
 		(0x1 << 11) | (0xf << 12), (0x1 << 11) | (0x9 << 12));
-	clrbits_le32(&ch[0].phy.misc_ctrl0, 0xf << 0);
-	setbits_le32(&ch[0].ao.shu[0].stbcal, 0x1 << 8);
-	setbits_le32(&ch[0].ao.stbcal, 0x1 << 17);
-	clrbits_le32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 14);
-	clrbits_le32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 14);
-	clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x7 << 4, 0x1 << 4);
+	clrbits32(&ch[0].phy.misc_ctrl0, 0xf << 0);
+	setbits32(&ch[0].ao.shu[0].stbcal, 0x1 << 8);
+	setbits32(&ch[0].ao.stbcal, 0x1 << 17);
+	clrbits32(&ch[0].phy.shu[0].b[0].dq[7], 0x1 << 14);
+	clrbits32(&ch[0].phy.shu[0].b[1].dq[7], 0x1 << 14);
+	clrsetbits32(&ch[0].ao.shu[0].stbcal, 0x7 << 4, 0x1 << 4);
 
 	if (freq_group == LP4X_DDR1600)
-		clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x0 << 0);
+		clrsetbits32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x0 << 0);
 	else
-		clrsetbits_le32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x2 << 0);
-	setbits_le32(&ch[0].ao.refctrl1, (0x1 << 0) | (0x1 << 5));
-	setbits_le32(&ch[0].ao.dqsoscr, (0x1 << 23) | (0x1 << 27));
-	clrbits_le32(&ch[0].ao.rstmask, (0x1 << 24) | (0x1 << 25) | (0x1 << 26));
-	clrsetbits_le32(&ch[0].ao.rkcfg, 0x7 << 4, 0x1 << 4);
+		clrsetbits32(&ch[0].ao.shu[0].stbcal, 0x3 << 0, 0x2 << 0);
+	setbits32(&ch[0].ao.refctrl1, (0x1 << 0) | (0x1 << 5));
+	setbits32(&ch[0].ao.dqsoscr, (0x1 << 23) | (0x1 << 27));
+	clrbits32(&ch[0].ao.rstmask, (0x1 << 24) | (0x1 << 25) | (0x1 << 26));
+	clrsetbits32(&ch[0].ao.rkcfg, 0x7 << 4, 0x1 << 4);
 	udelay(12);
 
-	clrsetbits_le32(&ch[0].ao.shu[0].rankctl,
+	clrsetbits32(&ch[0].ao.shu[0].rankctl,
 		(0xf << 24) | (0xf << 28), (0x4 << 24) | 0x6 << 28);
-	clrbits_le32(&ch[0].ao.shu[0].wodt, 0x1 << 31);
-	clrsetbits_le32(&ch[0].ao.shu[0].rk[0].fine_tune,
+	clrbits32(&ch[0].ao.shu[0].wodt, 0x1 << 31);
+	clrsetbits32(&ch[0].ao.shu[0].rk[0].fine_tune,
 		(0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24),
 		(0x1a << 0) | (0x1a << 8) | (0x1a << 16) | (0x1a << 24));
-	clrsetbits_le32(&ch[0].ao.shu[0].rk[1].fine_tune,
+	clrsetbits32(&ch[0].ao.shu[0].rk[1].fine_tune,
 		(0x3f << 0) | (0x3f << 8) | (0x3f << 16) | (0x3f << 24),
 		(0x14 << 0) | (0x14 << 8) | (0x14 << 16) | (0x14 << 24));
 	for (u8 rank = 0; rank < 2; rank++) {
-		clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[2],
+		clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[2],
 			(0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28),
 			(0x4 << 16) | (0x4 << 20) | (0x4 << 24) | (0x4 << 28));
-		clrsetbits_le32(&ch[0].ao.shu[0].rk[rank].selph_dq[3],
+		clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[3],
 			(0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28),
 			(0x4 << 16) | (0x4 << 20) | (0x4 << 24) | (0x4 << 28));
 	}
-	clrsetbits_le32(&ch[0].ao.shu[0].dqsg_retry,
+	clrsetbits32(&ch[0].ao.shu[0].dqsg_retry,
 		(0x1 << 2) | (0xf << 8) | (0x1 << 14) | (0x3 << 24),
 		(0x1 << 2) | (0x5 << 8) | (0x0 << 14) | (0x1 << 24));
-	setbits_le32(&ch[0].phy.shu[0].b[0].dq[7], (0x1 << 12) | (0x1 << 13));
-	setbits_le32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 12) | (0x1 << 13));
-	clrbits_le32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0);
+	setbits32(&ch[0].phy.shu[0].b[0].dq[7], (0x1 << 12) | (0x1 << 13));
+	setbits32(&ch[0].phy.shu[0].b[1].dq[7], (0x1 << 12) | (0x1 << 13));
+	clrbits32(&ch[0].ao.shu[0].dqs2dq_tx, 0x1f << 0);
 
 	switch (freq_group) {
 	case LP4X_DDR1600:
@@ -1407,28 +1407,28 @@ static void dramc_setting(const struct sdram_params *params, u8 freq_group,
 	update_initial_settings(freq_group);
 	dramc_sw_impedance_save_reg(freq_group, impedance);
 
-	clrbits_le32(&ch[0].ao.test2_4, 0x1 << 17);
-	clrsetbits_le32(&ch[0].ao.shu[0].conf[3], 0x1ff << 0, 0x5 << 0);
+	clrbits32(&ch[0].ao.test2_4, 0x1 << 17);
+	clrsetbits32(&ch[0].ao.shu[0].conf[3], 0x1ff << 0, 0x5 << 0);
 	udelay(1);
 
-	setbits_le32(&ch[0].ao.refctrl0, (0x1 << 17) | (0x1 << 18));
-	setbits_le32(&ch[0].ao.shuctrl2, (0x1 << 24) | (0x1 << 25));
-	setbits_le32(&ch[0].ao.refctrl0, 0x1 << 29);
-	setbits_le32(&ch[0].ao.dramctrl, 0x1 << 26);
-	clrsetbits_le32(&ch[0].ao.dummy_rd,
+	setbits32(&ch[0].ao.refctrl0, (0x1 << 17) | (0x1 << 18));
+	setbits32(&ch[0].ao.shuctrl2, (0x1 << 24) | (0x1 << 25));
+	setbits32(&ch[0].ao.refctrl0, 0x1 << 29);
+	setbits32(&ch[0].ao.dramctrl, 0x1 << 26);
+	clrsetbits32(&ch[0].ao.dummy_rd,
 		(0x1 << 4) | (0x1 << 11) | (0x1 << 13) |
 		(0x1 << 14) | (0x3 << 16) | (0x1 << 22),
 		(0x1 << 4) | (0x1 << 11) | (0x1 << 13) |
 		(0x1 << 14) | (0x2 << 16) | (0x1 << 22));
-	clrsetbits_le32(&ch[0].ao.test2_4, 0x7 << 28, 0x4 << 28);
-	clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 0);
+	clrsetbits32(&ch[0].ao.test2_4, 0x7 << 28, 0x4 << 28);
+	clrbits32(&ch[0].ao.dramctrl, 0x1 << 0);
 	udelay(1);
 
 	dramc_set_broadcast(DRAMC_BROADCAST_OFF);
-	clrsetbits_le32(&ch[0].ao.shuctrl, (0x1 << 5) | (0x1 << 17), (0x0 << 5) | (0x1 << 17));
-	setbits_le32(&ch[0].ao.shuctrl2, 0x1 << 12);
-	clrsetbits_le32(&ch[1].ao.shuctrl, (0x1 << 5) | (0x1 << 17), (0x1 << 5) | (0x0 << 17));
-	clrbits_le32(&ch[1].ao.shuctrl2, 0x1 << 12);
+	clrsetbits32(&ch[0].ao.shuctrl, (0x1 << 5) | (0x1 << 17), (0x0 << 5) | (0x1 << 17));
+	setbits32(&ch[0].ao.shuctrl2, 0x1 << 12);
+	clrsetbits32(&ch[1].ao.shuctrl, (0x1 << 5) | (0x1 << 17), (0x1 << 5) | (0x0 << 17));
+	clrbits32(&ch[1].ao.shuctrl2, 0x1 << 12);
 }
 
 struct ac_time {
@@ -1651,33 +1651,33 @@ static void ddr_update_ac_timing(u8 freq_group)
 	}
 
 	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
-		clrsetbits_le32(&ch[chn].ao.shu[0].actim[0],
+		clrsetbits32(&ch[chn].ao.shu[0].actim[0],
 			(0xf << 24) | (0x7 << 16) | (0x1f << 8) | (0xf << 0),
 			(ac_t.trcd << 24) | (ac_t.trrd << 16) |
 			(ac_t.twr << 8) | (ac_t.twtr << 0));
-		clrsetbits_le32(&ch[chn].ao.shu[0].actim[1],
+		clrsetbits32(&ch[chn].ao.shu[0].actim[1],
 			(0x1f << 24) | (0xf << 16) | (0xf << 8) | (0x7 << 0),
 			(ac_t.trc << 24) | (ac_t.tras << 16) |
 			(ac_t.trp << 8) | (ac_t.trpab << 0));
-		clrsetbits_le32(&ch[chn].ao.shu[0].actim[2],
+		clrsetbits32(&ch[chn].ao.shu[0].actim[2],
 			(0x1f << 24) | (0xf << 16) | (0x7 << 8) | (0x7 << 0),
 			(ac_t.tfaw << 24) | (trtw << 16) |
 			(ac_t.trtp << 8) | (ac_t.txp << 0));
-		clrsetbits_le32(&ch[chn].ao.shu[0].actim[3],
+		clrsetbits32(&ch[chn].ao.shu[0].actim[3],
 			(0xff << 16) | (0xff << 24) | (0xff << 0),
 			(ac_t.trfc << 16) | (ac_t.refcnt << 24) | (ac_t.trfcpb << 0));
-		clrsetbits_le32(&ch[chn].ao.shu[0].actim[4],
+		clrsetbits32(&ch[chn].ao.shu[0].actim[4],
 			(0xff << 24) | (0xff << 16) | (0x3ff << 0),
 			(ac_t.tzqcs << 24) | (ac_t.refcnt_fr_clk << 16) |
 			(ac_t.txrefcnt << 0));
-		clrsetbits_le32(&ch[chn].ao.shu[0].actim[5],
+		clrsetbits32(&ch[chn].ao.shu[0].actim[5],
 			(0xf << 24) | (0x1f << 8) | (0x1f << 0),
 			(tmrr2w << 24) | (ac_t.twtpd << 8) | (ac_t.trtpd << 0));
-		clrsetbits_le32(&ch[chn].ao.shu[0].actim_xrt,
+		clrsetbits32(&ch[chn].ao.shu[0].actim_xrt,
 			(0xf << 24) | (0x7 << 16) | (0xf << 8) | (0x1f << 0),
 			(ac_t.xrtw2w << 24) | (ac_t.xrtw2r << 16) |
 			(ac_t.xrtr2w << 8) | (ac_t.xrtr2r << 0));
-		clrsetbits_le32(&ch[chn].ao.shu[0].ac_time_05t,
+		clrsetbits32(&ch[chn].ao.shu[0].ac_time_05t,
 			(0x1 << 25) | (0x0 << 24) | (0x1 << 16) | (0x0 << 15) |
 			(0x1 << 13) | (0x1 << 12) | (0x1 << 10) | (0x1 << 9) |
 			(0x1 << 8) | (0x1 << 7) | (0x1 << 6) | (0x1 << 5) |
@@ -1690,45 +1690,45 @@ static void ddr_update_ac_timing(u8 freq_group)
 			(ac_t.trcd_05T << 6) | (ac_t.trtp_05T << 5) |
 			(ac_t.txp_05T << 4) | (ac_t.trfc_05T << 2) |
 			(ac_t.trfcpb_05T << 1) | (ac_t.trc_05T << 0));
-		clrsetbits_le32(&ch[chn].ao.catraining1, (0xff << 24) | (0xf << 20),
+		clrsetbits32(&ch[chn].ao.catraining1, (0xff << 24) | (0xf << 20),
 			(ac_t.r_dmcatrain_intv << 24) | (0x0 << 20));
 
 		/* DQSINCTL related */
-		clrsetbits_le32(&ch[chn].ao.shu[0].rk[0].dqsctl, 0xf << 0,
+		clrsetbits32(&ch[chn].ao.shu[0].rk[0].dqsctl, 0xf << 0,
 			ac_t.dqsinctl << 0);
-		clrsetbits_le32(&ch[chn].ao.shu[0].rk[1].dqsctl, 0xf << 0,
+		clrsetbits32(&ch[chn].ao.shu[0].rk[1].dqsctl, 0xf << 0,
 			ac_t.dqsinctl << 0);
-		clrsetbits_le32(&ch[chn].ao.shu[0].odtctrl, 0xf << 4,
+		clrsetbits32(&ch[chn].ao.shu[0].odtctrl, 0xf << 4,
 			ac_t.dqsinctl << 4);
 
 		/* DATLAT related, tREFBW */
-		clrsetbits_le32(&ch[chn].ao.shu[0].conf[1],
+		clrsetbits32(&ch[chn].ao.shu[0].conf[1],
 			(0x1f << 0) | (0x1f << 8) | (0x1f << 26) | (0x3ff << 16),
 			(ac_t.datlat << 0) | (new_datlat << 8) |
 			(new_datlat << 26) | (0x0 << 16));
-		clrsetbits_le32(&ch[chn].ao.shu[0].conf[2],
+		clrsetbits32(&ch[chn].ao.shu[0].conf[2],
 			(0xff << 8), ac_t.r_dmfspchg_prdcnt << 8);
-		clrsetbits_le32(&ch[chn].ao.shu[0].scintv, (0x1f << 13) | (0x1f << 6),
+		clrsetbits32(&ch[chn].ao.shu[0].scintv, (0x1f << 13) | (0x1f << 6),
 			(ac_t.r_dmmrw_intv << 13) | (ac_t.zqlat2 << 6));
 
 		/* CKEPRD - CKE pulse width */
-		clrsetbits_le32(&ch[chn].ao.shu[0].ckectrl, 0x7 << 20, ac_t.ckeprd << 20);
+		clrsetbits32(&ch[chn].ao.shu[0].ckectrl, 0x7 << 20, ac_t.ckeprd << 20);
 
 		/* CKELCKCNT: Valid clock requirement after CKE input low */
-		clrsetbits_le32(&ch[chn].ao.ckectrl, 0x7 << 24, ac_t.ckelckcnt << 24);
+		clrsetbits32(&ch[chn].ao.ckectrl, 0x7 << 24, ac_t.ckelckcnt << 24);
 
 		temp = ((read32(&ch[chn].ao.shu[0].rankctl) & 0x00f00000) >> 20) & 0xf;
-		clrsetbits_le32(&ch[chn].ao.shu[0].rankctl, 0xf << 0, temp << 0);
+		clrsetbits32(&ch[chn].ao.shu[0].rankctl, 0xf << 0, temp << 0);
 
-		clrsetbits_le32(&ch[chn].ao.shu[0].rankctl,
+		clrsetbits32(&ch[chn].ao.shu[0].rankctl,
 			(0xf << 16) | (0xf << 12) | (0xf << 8),
 			(root << 16) | (tx_rank_inctl << 12) | (tx_dly << 8));
 	}
 
 	u8 dram_cbt_mode = 0;
-	clrsetbits_le32(&ch[0].ao.arbctl, 0x7 << 10, 0x3 << 10);
-	clrsetbits_le32(&ch[0].ao.rstmask, 0x3 << 13, dram_cbt_mode);
-	clrsetbits_le32(&ch[0].ao.arbctl, 0x1 << 13, dram_cbt_mode);
+	clrsetbits32(&ch[0].ao.arbctl, 0x7 << 10, 0x3 << 10);
+	clrsetbits32(&ch[0].ao.rstmask, 0x3 << 13, dram_cbt_mode);
+	clrsetbits32(&ch[0].ao.arbctl, 0x1 << 13, dram_cbt_mode);
 }
 
 void dramc_init(const struct sdram_params *params, u8 freq_group,
diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c
index eb30381953..1eb86f406f 100644
--- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c
+++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c
@@ -48,7 +48,7 @@ static void dramc_sw_imp_cal_vref_sel(u8 term_option, u8 impcal_stage)
 		}
 	}
 
-	clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x3f << 8, vref_sel << 8);
+	clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0x3f << 8, vref_sel << 8);
 }
 
 void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term,
@@ -60,29 +60,29 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term,
 	broadcast_bak = dramc_get_broadcast();
 	dramc_set_broadcast(DRAMC_BROADCAST_OFF);
 
-	clrbits_le32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0);
+	clrbits32(&ch[0].phy.misc_spm_ctrl1, 0xf << 0);
 	write32(&ch[0].phy.misc_spm_ctrl2, 0x0);
 	write32(&ch[0].phy.misc_spm_ctrl0, 0x0);
-	clrbits_le32(&ch[0].ao.impcal, 0x1 << 31);
+	clrbits32(&ch[0].ao.impcal, 0x1 << 31);
 
 	impcal_bak = read32(&ch[0].ao.impcal);
 	dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_DRVP);
-	clrbits_le32(&ch[0].phy.misc_imp_ctrl1, 0x1 << 6);
-	clrsetbits_le32(&ch[0].ao.impcal, 0x1 << 21, 0x3 << 24);
-	clrsetbits_le32(&ch[0].phy.misc_imp_ctrl0, 0x7 << 4, 0x3 << 4);
+	clrbits32(&ch[0].phy.misc_imp_ctrl1, 0x1 << 6);
+	clrsetbits32(&ch[0].ao.impcal, 0x1 << 21, 0x3 << 24);
+	clrsetbits32(&ch[0].phy.misc_imp_ctrl0, 0x7 << 4, 0x3 << 4);
 	udelay(1);
 
 	dramc_dbg("impedance: K DRVP\n");
-	setbits_le32(&ch[0].ao.impcal, 0x1 << 23);
-	setbits_le32(&ch[0].ao.impcal, 0x1 << 22);
-	clrbits_le32(&ch[0].ao.impcal, 0x1 << 21);
-	clrbits_le32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11);
-	clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3);
+	setbits32(&ch[0].ao.impcal, 0x1 << 23);
+	setbits32(&ch[0].ao.impcal, 0x1 << 22);
+	clrbits32(&ch[0].ao.impcal, 0x1 << 21);
+	clrbits32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11);
+	clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3);
 
 	for (u8 impx_drv = 0; impx_drv < 32; impx_drv++) {
 		impx_drv = (impx_drv == 16) ? 29 : impx_drv;
 
-		clrsetbits_le32(&ch[0].ao.shu[0].impcal1,
+		clrsetbits32(&ch[0].ao.shu[0].impcal1,
 				0x1f << 4, impx_drv << 4);
 		udelay(1);
 		imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >>
@@ -100,17 +100,17 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term,
 
 	dramc_dbg("impedance: K ODTN\n");
 	dramc_sw_imp_cal_vref_sel(term, IMPCAL_STAGE_DRVN);
-	clrbits_le32(&ch[0].ao.impcal, 0x1 << 22);
+	clrbits32(&ch[0].ao.impcal, 0x1 << 22);
 	if (term == ODT_ON)
-		setbits_le32(&ch[0].ao.impcal, 0x1 << 21);
-	clrsetbits_le32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11,
+		setbits32(&ch[0].ao.impcal, 0x1 << 21);
+	clrsetbits32(&ch[0].ao.shu[0].impcal1, 0x1f << 4 | 0x1f << 11,
 		DRVP_result << 4 | 0x1f << 11);
-	clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3);
+	clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff << 0, 0x3);
 
 	for (u8 impx_drv = 0; impx_drv < 32; impx_drv++) {
 		impx_drv = (impx_drv == 16) ? 29 : impx_drv;
 
-		clrsetbits_le32(&ch[0].ao.shu[0].impcal1,
+		clrsetbits32(&ch[0].ao.shu[0].impcal1,
 				0x1f << 11, impx_drv << 11);
 		udelay(1);
 		imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >>
@@ -163,31 +163,31 @@ void dramc_sw_impedance_save_reg(u8 freq_group,
 	sw_impedance[ODT_OFF][2] = sw_impedance[ODT_ON][2];
 	sw_impedance[ODT_OFF][3] = sw_impedance[ODT_ON][3];
 
-	clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0xff, 0x3);
+	clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0xff, 0x3);
 	dramc_sw_imp_cal_vref_sel(dq_term, IMPCAL_STAGE_DRVP);
 
 	/* DQ */
-	clrsetbits_le32(&ch[0].ao.shu[0].drving[0], (0x1f << 5) | (0x1f << 0),
+	clrsetbits32(&ch[0].ao.shu[0].drving[0], (0x1f << 5) | (0x1f << 0),
 		(sw_impedance[dq_term][0] << 5) |
 		(sw_impedance[dq_term][1] << 0));
-	clrsetbits_le32(&ch[0].ao.shu[0].drving[1],
+	clrsetbits32(&ch[0].ao.shu[0].drving[1],
 		(0x1f << 25) | (0x1f << 20) | (1 << 31),
 		(sw_impedance[dq_term][0] << 25) |
 		(sw_impedance[dq_term][1] << 20) | (!dq_term << 31));
-	clrsetbits_le32(&ch[0].ao.shu[0].drving[2], (0x1f << 5) | (0x1f << 0),
+	clrsetbits32(&ch[0].ao.shu[0].drving[2], (0x1f << 5) | (0x1f << 0),
 		(sw_impedance[dq_term][2] << 5) |
 		(sw_impedance[dq_term][3] << 0));
-	clrsetbits_le32(&ch[0].ao.shu[0].drving[3], (0x1f << 25) | (0x1f << 20),
+	clrsetbits32(&ch[0].ao.shu[0].drving[3], (0x1f << 25) | (0x1f << 20),
 		(sw_impedance[dq_term][2] << 25) |
 		(sw_impedance[dq_term][3] << 20));
 
 	/* DQS */
 	for (u8 i = 0; i <= 2; i += 2) {
-		clrsetbits_le32(&ch[0].ao.shu[0].drving[i],
+		clrsetbits32(&ch[0].ao.shu[0].drving[i],
 			(0x1f << 25) | (0x1f << 20),
 			(sw_impedance[dq_term][i] << 25) |
 			(sw_impedance[dq_term][i + 1] << 20));
-		clrsetbits_le32(&ch[0].ao.shu[0].drving[i],
+		clrsetbits32(&ch[0].ao.shu[0].drving[i],
 			(0x1f << 15) | (0x1f << 10),
 			(sw_impedance[dq_term][i] << 15) |
 			(sw_impedance[dq_term][i + 1] << 10));
@@ -195,19 +195,19 @@ void dramc_sw_impedance_save_reg(u8 freq_group,
 
 	/* CMD & CLK */
 	for (u8 i = 1; i <= 3; i += 2) {
-		clrsetbits_le32(&ch[0].ao.shu[0].drving[i],
+		clrsetbits32(&ch[0].ao.shu[0].drving[i],
 			(0x1f << 15) | (0x1f << 10),
 			(sw_impedance[ca_term][i - 1] << 15) |
 			(sw_impedance[ca_term][i] << 10));
-		clrsetbits_le32(&ch[0].ao.shu[0].drving[i],
+		clrsetbits32(&ch[0].ao.shu[0].drving[i],
 			(0x1f << 5) | (0x1f << 0),
 			(sw_impedance[ca_term][i - 1] << 5) |
 			(sw_impedance[ca_term][i] << 0));
 	}
 
-	clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 17,
+	clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 17,
 		sw_impedance[ca_term][0] << 17);
-	clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 22,
+	clrsetbits32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 22,
 		sw_impedance[ca_term][1] << 22);
 
 	SET32_BITFIELDS(&ch[0].phy.shu[0].ca_cmd[3],
@@ -215,34 +215,34 @@ void dramc_sw_impedance_save_reg(u8 freq_group,
 	SET32_BITFIELDS(&ch[0].phy.shu[0].ca_cmd[0],
 			SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE, 0);
 
-	clrsetbits_le32(&ch[0].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16);
+	clrsetbits32(&ch[0].phy.shu[0].ca_dll[1], 0x1f << 16, 0x9 << 16);
 }
 
 static void transfer_pll_to_spm_control(void)
 {
 	u8 shu_lev = (read32(&ch[0].ao.shustatus) >> 1) & 0x3;
 
-	clrsetbits_le32(&mtk_spm->poweron_config_set,
+	clrsetbits32(&mtk_spm->poweron_config_set,
 		(0xffff << 16) | (0x1 << 0),
 		(0xb16 << 16) | (0x1 << 0));
 
 	/* Set SPM pinmux */
-	clrbits_le32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16));
-	setbits_le32(&mtk_spm->dramc_dpy_clk_sw_con_sel, 0xffffffff);
-	setbits_le32(&mtk_spm->dramc_dpy_clk_sw_con_sel2, 0xffffffff);
+	clrbits32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16));
+	setbits32(&mtk_spm->dramc_dpy_clk_sw_con_sel, 0xffffffff);
+	setbits32(&mtk_spm->dramc_dpy_clk_sw_con_sel2, 0xffffffff);
 
-	setbits_le32(&mtk_spm->spm_power_on_val0, (0x1 << 8) | (0xf << 12));
-	setbits_le32(&mtk_spm->spm_s1_mode_ch, 0x3 << 0);
+	setbits32(&mtk_spm->spm_power_on_val0, (0x1 << 8) | (0xf << 12));
+	setbits32(&mtk_spm->spm_s1_mode_ch, 0x3 << 0);
 
 	shu_lev = (shu_lev == 1) ? 2 : 1;
-	clrsetbits_le32(&mtk_spm->spm_power_on_val0, 0x3 << 28, shu_lev << 28);
-	clrsetbits_le32(&mtk_spm->dramc_dpy_clk_sw_con2,
+	clrsetbits32(&mtk_spm->spm_power_on_val0, 0x3 << 28, shu_lev << 28);
+	clrsetbits32(&mtk_spm->dramc_dpy_clk_sw_con2,
 		0x3 << 2, shu_lev << 2);
 
 	udelay(1);
 	for (size_t chn = CHANNEL_A; chn < CHANNEL_MAX; chn++) {
-		clrbits_le32(&ch[chn].phy.pll1, 0x1 << 31);
-		clrbits_le32(&ch[chn].phy.pll2, 0x1 << 31);
+		clrbits32(&ch[chn].phy.pll1, 0x1 << 31);
+		clrbits32(&ch[chn].phy.pll2, 0x1 << 31);
 	}
 }
 
@@ -254,50 +254,50 @@ static void dramc_rx_input_delay_tracking(u8 chn)
 	/* DVS mode to RG mode */
 	for (size_t r = 0; r < 2; r++)
 		for (size_t b = 0; b < 2; b++)
-			clrbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[2], 3 << 30);
+			clrbits32(&ch[chn].phy.r[r].b[b].rxdvs[2], 3 << 30);
 
-	clrsetbits_le32(&ch[chn].phy.b0_rxdvs[0], 0x1 << 19, 0x1 << 9);
-	clrsetbits_le32(&ch[chn].phy.b1_rxdvs[0], 0x1 << 19, 0x1 << 9);
+	clrsetbits32(&ch[chn].phy.b0_rxdvs[0], 0x1 << 19, 0x1 << 9);
+	clrsetbits32(&ch[chn].phy.b1_rxdvs[0], 0x1 << 19, 0x1 << 9);
 
 	for (size_t r = 0; r < 2; r++)
 		for (size_t b = 0; b < 2; b++) {
-			clrbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[2], 1 << 29);
-			clrsetbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[7],
+			clrbits32(&ch[chn].phy.r[r].b[b].rxdvs[2], 1 << 29);
+			clrsetbits32(&ch[chn].phy.r[r].b[b].rxdvs[7],
 				(0x3f << 0) | (0x3f << 8) |
 				(0x7f << 16) | (0x7f << 24),
 				(0x0 << 0) | (0x3f << 8) |
 				(0x0 << 16) | (0x7f << 24));
-			clrsetbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[1],
+			clrsetbits32(&ch[chn].phy.r[r].b[b].rxdvs[1],
 				(0xffff << 16) | (0xffff << 0),
 				(0x2 << 16) | (0x2 << 0));
 
 			/* DQ/DQS Rx DLY adjustment for tracking mode */
-			clrbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[2],
+			clrbits32(&ch[chn].phy.r[r].b[b].rxdvs[2],
 				(0x3 << 26) | (0x3 << 24) |
 				(0x3 << 18) | (0x3 << 16));
 		}
 
 	/* Rx DLY tracking setting (Static) */
-	clrsetbits_le32(&ch[chn].phy.b0_rxdvs[0],
+	clrsetbits32(&ch[chn].phy.b0_rxdvs[0],
 		(0x1 << 29) | (0xf << 4) | (0x1 << 0),
 		(0x1 << 29) | (0x0 << 4) | (0x1 << 0));
-	clrsetbits_le32(&ch[chn].phy.b1_rxdvs[0],
+	clrsetbits32(&ch[chn].phy.b1_rxdvs[0],
 		(0x1 << 29) | (0xf << 4) | (0x1 << 0),
 		(0x1 << 29) | (0x0 << 4) | (0x1 << 0));
 
 	for (u8 b = 0; b < 2; b++) {
-		clrsetbits_le32(&ch[chn].phy.b[b].dq[9],
+		clrsetbits32(&ch[chn].phy.b[b].dq[9],
 			(0x7 << 28) | (0x7 << 24),
 			(0x1 << 28) | (0x0 << 24));
-		setbits_le32(&ch[chn].phy.b[b].dq[5], 0x1 << 31);
+		setbits32(&ch[chn].phy.b[b].dq[5], 0x1 << 31);
 	}
-	clrbits_le32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24));
+	clrbits32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24));
 
-	setbits_le32(&ch[chn].phy.b0_rxdvs[0], (0x1 << 28) | (0x1 << 31));
-	setbits_le32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 28) | (0x1 << 31));
+	setbits32(&ch[chn].phy.b0_rxdvs[0], (0x1 << 28) | (0x1 << 31));
+	setbits32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 28) | (0x1 << 31));
 	for (u8 rank = RANK_0; rank < RANK_MAX; rank++)
 		for (u8 b = 0; b < 2; b++)
-			clrsetbits_le32(&ch[chn].phy.r[rank].b[b].rxdvs[2],
+			clrsetbits32(&ch[chn].phy.r[rank].b[b].rxdvs[2],
 				(0x3 << 30) | (0x1 << 28) | (0x1 << 23),
 				(0x2 << 30) | (0x1 << 28) | (0x1 << 23));
 
@@ -305,29 +305,29 @@ static void dramc_rx_input_delay_tracking(u8 chn)
 
 static void dramc_hw_dqs_gating_tracking(u8 chn)
 {
-	clrsetbits_le32(&ch[chn].ao.stbcal,
+	clrsetbits32(&ch[chn].ao.stbcal,
 		(0x1 << 21) | (0x3 << 15) | (0x1f << 8) | (0x1 << 4),
 		(0x3 << 26) | (0x1 << 0));
-	clrsetbits_le32(&ch[chn].ao.stbcal1,
+	clrsetbits32(&ch[chn].ao.stbcal1,
 		(0xffff << 16) | (0x1 << 8) | (0x1 << 6),
 		(0x1 << 16) | (0x1 << 8) | (0x1 << 6));
 
-	clrsetbits_le32(&ch[chn].phy.misc_ctrl0,
+	clrsetbits32(&ch[chn].phy.misc_ctrl0,
 		(0x1 << 24) | (0x1f << 11) | (0xf << 0),
 		(0x1 << 24) | (0x0 << 11) | (0x0 << 0));
 
-	clrbits_le32(&ch[chn].phy.b[0].dq[6], 0x1 << 31);
-	clrbits_le32(&ch[chn].phy.b[1].dq[6], 0x1 << 31);
-	clrbits_le32(&ch[chn].phy.ca_cmd[6], 0x1 << 31);
+	clrbits32(&ch[chn].phy.b[0].dq[6], 0x1 << 31);
+	clrbits32(&ch[chn].phy.b[1].dq[6], 0x1 << 31);
+	clrbits32(&ch[chn].phy.ca_cmd[6], 0x1 << 31);
 }
 
 static void dramc_hw_gating_init(void)
 {
 	for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
-		clrbits_le32(&ch[chn].ao.stbcal,
+		clrbits32(&ch[chn].ao.stbcal,
 			(0x7 << 22) | (0x3 << 14) | (0x1 << 19) | (0x1 << 21));
-		setbits_le32(&ch[chn].ao.stbcal, (0x1 << 20) | (0x3 << 28));
-		setbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 24);
+		setbits32(&ch[chn].ao.stbcal, (0x1 << 20) | (0x3 << 28));
+		setbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 24);
 
 		dramc_hw_dqs_gating_tracking(chn);
 	}
@@ -335,28 +335,28 @@ static void dramc_hw_gating_init(void)
 
 static void dramc_impedance_tracking_enable(void)
 {
-	setbits_le32(&ch[0].phy.misc_ctrl0, 0x1 << 10);
+	setbits32(&ch[0].phy.misc_ctrl0, 0x1 << 10);
 	for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
-		setbits_le32(&ch[chn].ao.impcal, (0x1 << 31) | (0x1 << 29) |
+		setbits32(&ch[chn].ao.impcal, (0x1 << 31) | (0x1 << 29) |
 			(0x1 << 26) | (0x1 << 17) | (0x7 << 11));
-		clrbits_le32(&ch[chn].ao.impcal, 0x1 << 30);
-		setbits_le32(&ch[chn].phy.misc_ctrl0, 0x1 << 18);
-		setbits_le32(&ch[chn].ao.impcal, 0x1 << 19);
+		clrbits32(&ch[chn].ao.impcal, 0x1 << 30);
+		setbits32(&ch[chn].phy.misc_ctrl0, 0x1 << 18);
+		setbits32(&ch[chn].ao.impcal, 0x1 << 19);
 	}
-	setbits_le32(&ch[0].ao.impcal, 0x1 << 14);
+	setbits32(&ch[0].ao.impcal, 0x1 << 14);
 	for (size_t chn = 0; chn < CHANNEL_MAX; chn++)
-		setbits_le32(&ch[chn].ao.refctrl0, (0x1 << 2) | (0x1 << 3));
+		setbits32(&ch[chn].ao.refctrl0, (0x1 << 2) | (0x1 << 3));
 }
 
 static void dramc_phy_low_power_enable(void)
 {
 	for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
 		for (size_t b = 0; b < 2; b++) {
-			clrbits_le32(&ch[chn].phy.b[b].dll_fine_tune[2],
+			clrbits32(&ch[chn].phy.b[b].dll_fine_tune[2],
 				0x3fffff << 10);
 			write32(&ch[chn].phy.b[b].dll_fine_tune[3], 0x2e800);
 		}
-		clrsetbits_le32(&ch[chn].phy.ca_dll_fine_tune[2],
+		clrsetbits32(&ch[chn].phy.ca_dll_fine_tune[2],
 			0x3fffff << 10, 0x2 << 10);
 	}
 	write32(&ch[0].phy.ca_dll_fine_tune[3], 0xba000);
@@ -365,67 +365,67 @@ static void dramc_phy_low_power_enable(void)
 
 static void dramc_dummy_read_for_tracking_enable(u8 chn)
 {
-	setbits_le32(&ch[chn].ao.dummy_rd, 0x3 << 16);
+	setbits32(&ch[chn].ao.dummy_rd, 0x3 << 16);
 
 	for (size_t r = 0; r < 2; r++)
 		for (size_t i = 0; i < 4; i++)
 			write32(&ch[chn].ao.rk[r].dummy_rd_wdata[i],
 				0xaaaa5555);
 
-	clrsetbits_le32(&ch[chn].ao.test2_4, 0x7 << 28, 0x4 << 28);
+	clrsetbits32(&ch[chn].ao.test2_4, 0x7 << 28, 0x4 << 28);
 	for (size_t r = 0; r < 2; r++) {
-		clrsetbits_le32(&ch[chn].ao.rk[r].dummy_rd_adr,
+		clrsetbits32(&ch[chn].ao.rk[r].dummy_rd_adr,
 			(0x1ffff << 0) | (0x7ff << 17) | (0xf << 28),
 			(0xffff << 0) | (0x3f0 << 17));
-		clrbits_le32(&ch[chn].ao.rk[r].dummy_rd_bk, 0x7 << 0);
+		clrbits32(&ch[chn].ao.rk[r].dummy_rd_bk, 0x7 << 0);
 	}
 
-	clrbits_le32(&ch[chn].ao.dummy_rd, 0x1 << 25 | 0x1 << 20);
+	clrbits32(&ch[chn].ao.dummy_rd, 0x1 << 25 | 0x1 << 20);
 }
 
 static void dramc_set_CKE_2_rank_independent(u8 chn)
 {
-	clrsetbits_le32(&ch[chn].ao.rkcfg, (0x1 << 15) | (0x1 << 12), 0x1 << 2);
-	clrsetbits_le32(&ch[chn].ao.ckectrl,
+	clrsetbits32(&ch[chn].ao.rkcfg, (0x1 << 15) | (0x1 << 12), 0x1 << 2);
+	clrsetbits32(&ch[chn].ao.ckectrl,
 		(0x1 << 1) | (0xf << 8) | (0x7 << 13),
 		(0x4 << 8) | (0x2 << 13));
 
 	for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
-		setbits_le32(&ch[chn].ao.shu[shu].conf[2],
+		setbits32(&ch[chn].ao.shu[shu].conf[2],
 			(0x1 << 29) | (0x1 << 31));
-	clrbits_le32(&ch[chn].ao.dramctrl, 0x1 << 9);
+	clrbits32(&ch[chn].ao.dramctrl, 0x1 << 9);
 }
 
 static void dramc_pa_improve(u8 chn)
 {
-	clrbits_le32(&ch[chn].ao.clkar, 0xffff);
-	clrbits_le32(&ch[chn].ao.srefctrl, 0xf << 12);
-	clrbits_le32(&ch[chn].ao.zqcs, 0x1 << 19);
-	clrbits_le32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17);
-	clrbits_le32(&ch[chn].ao.zqcs, 0x1 << 19);
-	clrbits_le32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17);
+	clrbits32(&ch[chn].ao.clkar, 0xffff);
+	clrbits32(&ch[chn].ao.srefctrl, 0xf << 12);
+	clrbits32(&ch[chn].ao.zqcs, 0x1 << 19);
+	clrbits32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17);
+	clrbits32(&ch[chn].ao.zqcs, 0x1 << 19);
+	clrbits32(&ch[chn].ao.pre_tdqsck[0], 0x1 << 17);
 
 	for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
-		clrbits_le32(&ch[chn].ao.shu[shu].odtctrl, 0x3 << 2);
+		clrbits32(&ch[chn].ao.shu[shu].odtctrl, 0x3 << 2);
 }
 
 static void dramc_enable_dramc_dcm(void)
 {
 	for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
-		clrsetbits_le32(&ch[chn].ao.dramc_pd_ctrl,
+		clrsetbits32(&ch[chn].ao.dramc_pd_ctrl,
 			(0x7 << 0) | (0x1 << 26) | (0x1 << 30) | (0x1 << 31),
 			(0x7 << 0) | (0x1 << 30) | (0x1 << 31));
-		setbits_le32(&ch[chn].ao.clkar, 0x1 << 31);
+		setbits32(&ch[chn].ao.clkar, 0x1 << 31);
 	}
 }
 
 void dramc_runtime_config(void)
 {
-	clrbits_le32(&ch[0].ao.refctrl0, 0x1 << 29);
-	clrbits_le32(&ch[1].ao.refctrl0, 0x1 << 29);
+	clrbits32(&ch[0].ao.refctrl0, 0x1 << 29);
+	clrbits32(&ch[1].ao.refctrl0, 0x1 << 29);
 
 	transfer_pll_to_spm_control();
-	setbits_le32(&mtk_spm->spm_power_on_val0, 0x1 << 25);
+	setbits32(&mtk_spm->spm_power_on_val0, 0x1 << 25);
 
 	/* RX_TRACKING: ON */
 	for (u8 chn = 0; chn < CHANNEL_MAX; chn++)
@@ -438,7 +438,7 @@ void dramc_runtime_config(void)
 
 	/* HW_GATING DBG: OFF */
 	for (size_t chn = 0; chn < CHANNEL_MAX; chn++)
-		clrbits_le32(&ch[chn].ao.stbcal2,
+		clrbits32(&ch[chn].ao.stbcal2,
 			(0x3 << 4) | (0x3 << 8) | (0x1 << 28));
 
 	/* DUMMY_READ_FOR_TRACKING: ON */
@@ -446,8 +446,8 @@ void dramc_runtime_config(void)
 		dramc_dummy_read_for_tracking_enable(chn);
 
 	/* ZQCS_ENABLE_LP4: ON */
-	clrbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 30);
-	clrbits_le32(&ch[1].ao.spcmdctrl, 0x1 << 30);
+	clrbits32(&ch[0].ao.spcmdctrl, 0x1 << 30);
+	clrbits32(&ch[1].ao.spcmdctrl, 0x1 << 30);
 
 	/* LOWPOWER_GOLDEN_SETTINGS(DCM): ON */
 	dramc_phy_low_power_enable();
@@ -456,7 +456,7 @@ void dramc_runtime_config(void)
 	/* DUMMY_READ_FOR_DQS_GATING_RETRY: OFF */
 	for (size_t chn = 0; chn < CHANNEL_MAX; chn++)
 		for (size_t shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
-			clrbits_le32(&ch[chn].ao.shu[shu].dqsg_retry,
+			clrbits32(&ch[chn].ao.shu[shu].dqsg_retry,
 				(0x1 << 1) | (0x3 << 13));
 
 	/* SPM_CONTROL_AFTERK: ON */
@@ -470,33 +470,33 @@ void dramc_runtime_config(void)
 
 	for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
 		/* TEMP_SENSOR: ON */
-		clrbits_le32(&ch[chn].ao.spcmdctrl, 0x3 << 28);
-		setbits_le32(&ch[chn].ao.hw_mrr_fun, (0x1 << 0) | (0x1 << 11));
+		clrbits32(&ch[chn].ao.spcmdctrl, 0x3 << 28);
+		setbits32(&ch[chn].ao.hw_mrr_fun, (0x1 << 0) | (0x1 << 11));
 
 		/* PER_BANK_REFRESH: ON */
-		clrbits_le32(&ch[chn].ao.refctrl0, 0x1 << 18);
+		clrbits32(&ch[chn].ao.refctrl0, 0x1 << 18);
 
 		/* HW_SAVE_FOR_SR: ON */
-		clrbits_le32(&ch[chn].ao.rstmask, (0x1 << 25) | (0x1 << 28));
-		setbits_le32(&ch[chn].ao.refctrl1, 0x1 << 0);
-		clrsetbits_le32(&ch[chn].ao.srefctrl, 0x1 << 20, 0x1 << 22);
+		clrbits32(&ch[chn].ao.rstmask, (0x1 << 25) | (0x1 << 28));
+		setbits32(&ch[chn].ao.refctrl1, 0x1 << 0);
+		clrsetbits32(&ch[chn].ao.srefctrl, 0x1 << 20, 0x1 << 22);
 
 		/* SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON */
 		dramc_set_CKE_2_rank_independent(chn);
 
 		/* CLK_FREE_FUN_FOR_DRAMC_PSEL: ON */
-		clrbits_le32(&ch[chn].ao.refctrl1, (0x1 << 6) | (0x3 << 2));
-		clrbits_le32(&ch[chn].ao.clkar, 0x1 << 19);
+		clrbits32(&ch[chn].ao.refctrl1, (0x1 << 6) | (0x3 << 2));
+		clrbits32(&ch[chn].ao.clkar, 0x1 << 19);
 
 		/* PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON */
 		dramc_pa_improve(chn);
 
 		/* DRAM DRS DISABLE */
-		clrsetbits_le32(&ch[chn].ao.drsctrl,
+		clrsetbits32(&ch[chn].ao.drsctrl,
 			(0x1 << 21) | (0x3f << 12) | (0xf << 8) | (0x1 << 6),
 			(0x1 << 19) | (0x3 << 12) | (0x8 << 8) |
 			(0x3 << 4) | (0x1 << 2) | (0x1 << 0));
-		setbits_le32(&ch[chn].ao.dummy_rd, 0x3 << 26);
+		setbits32(&ch[chn].ao.dummy_rd, 0x3 << 26);
 	}
 
 	enable_emi_dcm();
diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
index 16f28785d3..cd9f328ae6 100644
--- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
+++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c
@@ -154,8 +154,8 @@ static void move_dramc_delay(u32 *reg_0, u32 *reg_1, u8 shift, s8 shift_coarse_t
 		tmp_0p5t = sum - (tmp_2t << DQ_DIV_SHIFT);
 	}
 
-	clrsetbits_le32(reg_0, DQ_DIV_MASK << shift, tmp_0p5t << shift);
-	clrsetbits_le32(reg_1, DQ_DIV_MASK << shift, tmp_2t << shift);
+	clrsetbits32(reg_0, DQ_DIV_MASK << shift, tmp_0p5t << shift);
+	clrsetbits32(reg_1, DQ_DIV_MASK << shift, tmp_2t << shift);
 }
 
 static void move_dramc_tx_dqs(u8 chn, u8 byte, s8 shift_coarse_tune)
@@ -279,36 +279,36 @@ static void dramc_write_dbi_onoff(bool onoff)
 
 static void dramc_phy_dcm_2_channel(u8 chn, bool en)
 {
-	clrsetbits_le32(&ch[chn].phy.misc_cg_ctrl0, (0x3 << 19) | (0x3ff << 8),
+	clrsetbits32(&ch[chn].phy.misc_cg_ctrl0, (0x3 << 19) | (0x3ff << 8),
 		((en ? 0 : 0x1) << 19) | ((en ? 0 : 0x1ff) << 9) | (1 << 8));
 
 	for (size_t i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) {
 		struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[i];
 		for (size_t b = 0; b < 2; b++)
-			clrsetbits_le32(&shu->b[b].dq[8], 0x1fff << 19,
+			clrsetbits32(&shu->b[b].dq[8], 0x1fff << 19,
 				((en ? 0 : 0x7ff) << 22) | (0x1 << 21) |
 				((en ? 0 : 0x3) << 19));
-		clrbits_le32(&shu->ca_cmd[8], 0x1fff << 19);
+		clrbits32(&shu->ca_cmd[8], 0x1fff << 19);
 	}
-	clrsetbits_le32(&ch[chn].phy.misc_cg_ctrl5, (0x7 << 16) | (0x7 << 20),
+	clrsetbits32(&ch[chn].phy.misc_cg_ctrl5, (0x7 << 16) | (0x7 << 20),
 		((en ? 0x7 : 0) << 16) | ((en ? 0x7 : 0) << 20));
 }
 
 void dramc_enable_phy_dcm(bool en)
 {
 	for (size_t chn = 0; chn < CHANNEL_MAX ; chn++) {
-		clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 20);
-		clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 20);
-		clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[1], 0x1 << 20);
+		clrbits32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 20);
+		clrbits32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 20);
+		clrbits32(&ch[chn].phy.ca_dll_fine_tune[1], 0x1 << 20);
 
 		for (size_t i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) {
 			struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[i];
-			setbits_le32(&shu->b[0].dll[0], 0x1);
-			setbits_le32(&shu->b[1].dll[0], 0x1);
-			setbits_le32(&shu->ca_dll[0], 0x1);
+			setbits32(&shu->b[0].dll[0], 0x1);
+			setbits32(&shu->b[1].dll[0], 0x1);
+			setbits32(&shu->ca_dll[0], 0x1);
 		}
 
-		clrsetbits_le32(&ch[chn].ao.dramc_pd_ctrl,
+		clrsetbits32(&ch[chn].ao.dramc_pd_ctrl,
 			(0x1 << 0) | (0x1 << 1) | (0x1 << 2) |
 			(0x1 << 5) | (0x1 << 26) | (0x1 << 30) | (0x1 << 31),
 			((en ? 0x1 : 0) << 0) | ((en ? 0x1 : 0) << 1) |
@@ -324,16 +324,16 @@ void dramc_enable_phy_dcm(bool en)
 		write32(&ch[chn].phy.misc_cg_ctrl2,
 			0x8060033e | (0x40 << (en ? 0x1 : 0)));
 
-		clrsetbits_le32(&ch[chn].phy.misc_ctrl3, 0x3 << 26,
+		clrsetbits32(&ch[chn].phy.misc_ctrl3, 0x3 << 26,
 			(en ? 0 : 0x3) << 26);
 		for (size_t i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) {
 			u32 mask = 0x7 << 17;
 			u32 value = (en ? 0x7 : 0) << 17;
 			struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[i];
 
-			clrsetbits_le32(&shu->b[0].dq[7], mask, value);
-			clrsetbits_le32(&shu->b[1].dq[7], mask, value);
-			clrsetbits_le32(&shu->ca_cmd[7], mask, value);
+			clrsetbits32(&shu->b[0].dq[7], mask, value);
+			clrsetbits32(&shu->b[1].dq[7], mask, value);
+			clrsetbits32(&shu->ca_cmd[7], mask, value);
 		}
 
 		dramc_phy_dcm_2_channel(chn, en);
@@ -346,31 +346,31 @@ static void dramc_reset_delay_chain_before_calibration(void)
 		for (size_t rank = 0; rank < RANK_MAX; rank++) {
 			struct dramc_ddrphy_regs_shu_rk *rk;
 			rk = &ch[chn].phy.shu[0].rk[rank];
-			clrbits_le32(&rk->ca_cmd[0], 0xffffff << 0);
-			clrbits_le32(&rk->b[0].dq[0], 0xfffffff << 0);
-			clrbits_le32(&rk->b[1].dq[0], 0xfffffff << 0);
-			clrbits_le32(&rk->b[0].dq[1], 0xf << 0);
-			clrbits_le32(&rk->b[1].dq[1], 0xf << 0);
+			clrbits32(&rk->ca_cmd[0], 0xffffff << 0);
+			clrbits32(&rk->b[0].dq[0], 0xfffffff << 0);
+			clrbits32(&rk->b[1].dq[0], 0xfffffff << 0);
+			clrbits32(&rk->b[0].dq[1], 0xf << 0);
+			clrbits32(&rk->b[1].dq[1], 0xf << 0);
 		}
 }
 
 void dramc_hw_gating_onoff(u8 chn, bool on)
 {
-	clrsetbits_le32(&ch[chn].ao.shuctrl2, 0x3 << 14,
+	clrsetbits32(&ch[chn].ao.shuctrl2, 0x3 << 14,
 		(on ? 0x3 : 0) << 14);
-	clrsetbits_le32(&ch[chn].ao.stbcal2, 0x1 << 28, (on ? 0x1 : 0) << 28);
-	clrsetbits_le32(&ch[chn].ao.stbcal, 0x1 << 24, (on ? 0x1 : 0) << 24);
-	clrsetbits_le32(&ch[chn].ao.stbcal, 0x1 << 22, (on ? 0x1 : 0) << 22);
+	clrsetbits32(&ch[chn].ao.stbcal2, 0x1 << 28, (on ? 0x1 : 0) << 28);
+	clrsetbits32(&ch[chn].ao.stbcal, 0x1 << 24, (on ? 0x1 : 0) << 24);
+	clrsetbits32(&ch[chn].ao.stbcal, 0x1 << 22, (on ? 0x1 : 0) << 22);
 }
 
 static void dramc_rx_input_delay_tracking_init_by_freq(u8 chn)
 {
 	struct ddrphy_ao_shu *shu = &ch[chn].phy.shu[0];
 
-	clrsetbits_le32(&shu->b[0].dq[5], 0x7 << 20, 0x3 << 20);
-	clrsetbits_le32(&shu->b[1].dq[5], 0x7 << 20, 0x3 << 20);
-	clrbits_le32(&shu->b[0].dq[7], (0x1 << 12) | (0x1 << 13));
-	clrbits_le32(&shu->b[1].dq[7], (0x1 << 12) | (0x1 << 13));
+	clrsetbits32(&shu->b[0].dq[5], 0x7 << 20, 0x3 << 20);
+	clrsetbits32(&shu->b[1].dq[5], 0x7 << 20, 0x3 << 20);
+	clrbits32(&shu->b[0].dq[7], (0x1 << 12) | (0x1 << 13));
+	clrbits32(&shu->b[1].dq[7], (0x1 << 12) | (0x1 << 13));
 }
 
 void dramc_apply_config_before_calibration(u8 freq_group)
@@ -378,55 +378,55 @@ void dramc_apply_config_before_calibration(u8 freq_group)
 	dramc_enable_phy_dcm(false);
 	dramc_reset_delay_chain_before_calibration();
 
-	setbits_le32(&ch[0].ao.shu[0].conf[3], 0x1ff << 16);
-	setbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 24);
-	clrsetbits_le32(&ch[0].ao.shu[0].scintv, 0x1f << 1, 0x1b << 1);
+	setbits32(&ch[0].ao.shu[0].conf[3], 0x1ff << 16);
+	setbits32(&ch[0].ao.spcmdctrl, 0x1 << 24);
+	clrsetbits32(&ch[0].ao.shu[0].scintv, 0x1f << 1, 0x1b << 1);
 
 	for (size_t shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
-		setbits_le32(&ch[0].ao.shu[shu].conf[3], 0x1ff << 0);
+		setbits32(&ch[0].ao.shu[shu].conf[3], 0x1ff << 0);
 
-	clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 18);
-	clrbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 31);
-	clrbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 30);
-	clrbits_le32(&ch[0].ao.dqsoscr, 0x1 << 26);
-	clrbits_le32(&ch[0].ao.dqsoscr, 0x1 << 25);
+	clrbits32(&ch[0].ao.dramctrl, 0x1 << 18);
+	clrbits32(&ch[0].ao.spcmdctrl, 0x1 << 31);
+	clrbits32(&ch[0].ao.spcmdctrl, 0x1 << 30);
+	clrbits32(&ch[0].ao.dqsoscr, 0x1 << 26);
+	clrbits32(&ch[0].ao.dqsoscr, 0x1 << 25);
 
 	dramc_write_dbi_onoff(false);
 	dramc_read_dbi_onoff(false);
 
 	for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
-		setbits_le32(&ch[chn].ao.spcmdctrl, 0x1 << 29);
-		setbits_le32(&ch[chn].ao.dqsoscr, 0x1 << 24);
+		setbits32(&ch[chn].ao.spcmdctrl, 0x1 << 29);
+		setbits32(&ch[chn].ao.dqsoscr, 0x1 << 24);
 		for (size_t shu = DRAM_DFS_SHUFFLE_1; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
-			setbits_le32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30);
+			setbits32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30);
 
-		clrbits_le32(&ch[chn].ao.dummy_rd, (0x1 << 7) | (0x7 << 20));
+		clrbits32(&ch[chn].ao.dummy_rd, (0x1 << 7) | (0x7 << 20));
 		dramc_hw_gating_onoff(chn, false);
-		clrbits_le32(&ch[chn].ao.stbcal2, 0x1 << 28);
+		clrbits32(&ch[chn].ao.stbcal2, 0x1 << 28);
 
-		setbits_le32(&ch[chn].phy.misc_ctrl1, (0x1 << 7) | (0x1 << 11));
-		clrbits_le32(&ch[chn].ao.refctrl0, 0x1 << 18);
-		clrbits_le32(&ch[chn].ao.mrs, 0x3 << 24);
-		setbits_le32(&ch[chn].ao.mpc_option, 0x1 << 17);
-		clrsetbits_le32(&ch[chn].phy.b[0].dq[6], 0x3 << 0, 0x1 << 0);
-		clrsetbits_le32(&ch[chn].phy.b[1].dq[6], 0x3 << 0, 0x1 << 0);
-		clrsetbits_le32(&ch[chn].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0);
+		setbits32(&ch[chn].phy.misc_ctrl1, (0x1 << 7) | (0x1 << 11));
+		clrbits32(&ch[chn].ao.refctrl0, 0x1 << 18);
+		clrbits32(&ch[chn].ao.mrs, 0x3 << 24);
+		setbits32(&ch[chn].ao.mpc_option, 0x1 << 17);
+		clrsetbits32(&ch[chn].phy.b[0].dq[6], 0x3 << 0, 0x1 << 0);
+		clrsetbits32(&ch[chn].phy.b[1].dq[6], 0x3 << 0, 0x1 << 0);
+		clrsetbits32(&ch[chn].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0);
 
 		dramc_rx_input_delay_tracking_init_by_freq(chn);
 
-		setbits_le32(&ch[chn].ao.dummy_rd, 0x1 << 25);
-		setbits_le32(&ch[chn].ao.drsctrl, 0x1 << 0);
+		setbits32(&ch[chn].ao.dummy_rd, 0x1 << 25);
+		setbits32(&ch[chn].ao.drsctrl, 0x1 << 0);
 		if (freq_group == LP4X_DDR3200 || freq_group == LP4X_DDR3600)
-			clrbits_le32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31);
+			clrbits32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31);
 		else
-			setbits_le32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31);
+			setbits32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31);
 	}
 
 	for (size_t r = 0; r < 2; r++) {
 		for (size_t b = 0; b < 2; b++)
-			clrbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2],
+			clrbits32(&ch[0].phy.r[r].b[b].rxdvs[2],
 				(0x1 << 28) | (0x1 << 23) | (0x3 << 30));
-		clrbits_le32(&ch[0].phy.r0_ca_rxdvs[2], 0x3 << 30);
+		clrbits32(&ch[0].phy.r0_ca_rxdvs[2], 0x3 << 30);
 	}
 }
 
@@ -437,51 +437,51 @@ static void dramc_set_mr13_vrcg_to_Normal(u8 chn, const struct mr_value *mr)
 					     mr->MR13Value & ~(0x1 << 3));
 
 	for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
-		clrbits_le32(&ch[chn].ao.shu[shu].hwset_vrcg, 0x1 << 19);
+		clrbits32(&ch[chn].ao.shu[shu].hwset_vrcg, 0x1 << 19);
 }
 
 void dramc_apply_config_after_calibration(const struct mr_value *mr)
 {
 	for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
 		write32(&ch[chn].phy.misc_cg_ctrl4, 0x11400000);
-		clrbits_le32(&ch[chn].ao.refctrl1, 0x1 << 7);
-		clrbits_le32(&ch[chn].ao.shuctrl, 0x1 << 2);
-		clrbits_le32(&ch[chn].phy.ca_cmd[6], 0x1 << 6);
+		clrbits32(&ch[chn].ao.refctrl1, 0x1 << 7);
+		clrbits32(&ch[chn].ao.shuctrl, 0x1 << 2);
+		clrbits32(&ch[chn].phy.ca_cmd[6], 0x1 << 6);
 		dramc_set_mr13_vrcg_to_Normal(chn, mr);
 
-		clrbits_le32(&ch[chn].phy.b[0].dq[6], 0x3);
-		clrbits_le32(&ch[chn].phy.b[1].dq[6], 0x3);
-		clrbits_le32(&ch[chn].phy.ca_cmd[6], 0x3);
-		setbits_le32(&ch[chn].phy.b[0].dq[6], 0x1 << 5);
-		setbits_le32(&ch[chn].phy.b[1].dq[6], 0x1 << 5);
-		setbits_le32(&ch[chn].phy.ca_cmd[6], 0x1 << 5);
+		clrbits32(&ch[chn].phy.b[0].dq[6], 0x3);
+		clrbits32(&ch[chn].phy.b[1].dq[6], 0x3);
+		clrbits32(&ch[chn].phy.ca_cmd[6], 0x3);
+		setbits32(&ch[chn].phy.b[0].dq[6], 0x1 << 5);
+		setbits32(&ch[chn].phy.b[1].dq[6], 0x1 << 5);
+		setbits32(&ch[chn].phy.ca_cmd[6], 0x1 << 5);
 
-		clrbits_le32(&ch[chn].ao.impcal, 0x3 << 24);
-		clrbits_le32(&ch[chn].phy.misc_imp_ctrl0, 0x4);
-		clrbits_le32(&ch[chn].phy.misc_cg_ctrl0, 0xf);
+		clrbits32(&ch[chn].ao.impcal, 0x3 << 24);
+		clrbits32(&ch[chn].phy.misc_imp_ctrl0, 0x4);
+		clrbits32(&ch[chn].phy.misc_cg_ctrl0, 0xf);
 
-		clrbits_le32(&ch[chn].phy.misc_ctrl0, 0x1 << 31);
-		clrbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 25);
+		clrbits32(&ch[chn].phy.misc_ctrl0, 0x1 << 31);
+		clrbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 25);
 
-		setbits_le32(&ch[chn].ao.spcmdctrl, 1 << 29);
-		setbits_le32(&ch[chn].ao.dqsoscr, 1 << 24);
+		setbits32(&ch[chn].ao.spcmdctrl, 1 << 29);
+		setbits32(&ch[chn].ao.dqsoscr, 1 << 24);
 
 		for (u8 shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++)
-			clrbits_le32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30);
+			clrbits32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30);
 
-		clrbits_le32(&ch[chn].ao.dummy_rd, (0x7 << 20) | (0x1 << 7));
+		clrbits32(&ch[chn].ao.dummy_rd, (0x7 << 20) | (0x1 << 7));
 		dramc_cke_fix_onoff(chn, false, false);
-		clrbits_le32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26);
+		clrbits32(&ch[chn].ao.dramc_pd_ctrl, 0x1 << 26);
 
-		clrbits_le32(&ch[chn].ao.eyescan, 0x7 << 8);
-		clrsetbits_le32(&ch[chn].ao.test2_4, 0x7 << 28, 0x4 << 28);
+		clrbits32(&ch[chn].ao.eyescan, 0x7 << 8);
+		clrsetbits32(&ch[chn].ao.test2_4, 0x7 << 28, 0x4 << 28);
 	}
 }
 
 static void dramc_rx_dqs_isi_pulse_cg_switch(u8 chn, bool flag)
 {
 	for (size_t b = 0; b < 2; b++)
-		clrsetbits_le32(&ch[chn].phy.b[b].dq[6], 1 << 5,
+		clrsetbits32(&ch[chn].phy.b[b].dq[6], 1 << 5,
 				(flag ? 1 : 0) << 5);
 }
 
@@ -600,7 +600,7 @@ static u32 dramc_engine2_run(u8 chn, enum dram_te_op wr)
 
 static void dramc_engine2_end(u8 chn, u32 dummy_rd)
 {
-	clrbits_le32(&ch[chn].ao.test2_4, 0x1 << 17);
+	clrbits32(&ch[chn].ao.test2_4, 0x1 << 17);
 	write32(&ch[chn].ao.dummy_rd, dummy_rd);
 }
 
@@ -717,12 +717,12 @@ static void dram_phy_reset(u8 chn)
 {
 	SET32_BITFIELDS(&ch[chn].ao.ddrconf0, DDRCONF0_RDATRST, 1);
 	SET32_BITFIELDS(&ch[chn].phy.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 1);
-	clrbits_le32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0));
-	clrbits_le32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0));
+	clrbits32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0));
+	clrbits32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0));
 
 	udelay(1);
-	setbits_le32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0));
-	setbits_le32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0));
+	setbits32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0));
+	setbits32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0));
 	SET32_BITFIELDS(&ch[chn].phy.misc_ctrl1, MISC_CTRL1_R_DMPHYRST, 0);
 	SET32_BITFIELDS(&ch[chn].ao.ddrconf0, DDRCONF0_RDATRST, 0);
 }
@@ -737,18 +737,18 @@ static void dramc_set_gating_mode(u8 chn, bool mode)
 	}
 
 	for (size_t b = 0; b < 2; b++) {
-		clrsetbits_le32(&ch[chn].phy.b[b].dq[6], 0x3 << 14, vref << 14);
-		setbits_le32(&ch[chn].phy.b[b].dq[9], 0x1 << 5);
+		clrsetbits32(&ch[chn].phy.b[b].dq[6], 0x3 << 14, vref << 14);
+		setbits32(&ch[chn].phy.b[b].dq[9], 0x1 << 5);
 	}
 
-	clrsetbits_le32(&ch[chn].ao.stbcal1, 0x1 << 5, burst << 5);
-	setbits_le32(&ch[chn].ao.stbcal, 0x1 << 30);
+	clrsetbits32(&ch[chn].ao.stbcal1, 0x1 << 5, burst << 5);
+	setbits32(&ch[chn].ao.stbcal, 0x1 << 30);
 
-	clrbits_le32(&ch[chn].phy.b[0].dq[9], (0x1 << 4) | (0x1 << 0));
-	clrbits_le32(&ch[chn].phy.b[1].dq[9], (0x1 << 4) | (0x1 << 0));
+	clrbits32(&ch[chn].phy.b[0].dq[9], (0x1 << 4) | (0x1 << 0));
+	clrbits32(&ch[chn].phy.b[1].dq[9], (0x1 << 4) | (0x1 << 0));
 	udelay(1);
-	setbits_le32(&ch[chn].phy.b[1].dq[9], (0x1 << 4) | (0x1 << 0));
-	setbits_le32(&ch[chn].phy.b[0].dq[9], (0x1 << 4) | (0x1 << 0));
+	setbits32(&ch[chn].phy.b[1].dq[9], (0x1 << 4) | (0x1 << 0));
+	setbits32(&ch[chn].phy.b[0].dq[9], (0x1 << 4) | (0x1 << 0));
 }
 
 static void dramc_rx_dqs_gating_cal_pre(u8 chn, u8 rank)
@@ -773,7 +773,7 @@ static void dramc_rx_dqs_gating_cal_pre(u8 chn, u8 rank)
 
 static void set_selph_gating_value(uint32_t *addr, u8 dly, u8 dly_p1)
 {
-	clrsetbits_le32(addr, 0x77777777,
+	clrsetbits32(addr, 0x77777777,
 		(dly << 0) | (dly << 8) | (dly << 16) | (dly << 24) |
 		(dly_p1 << 4) | (dly_p1 << 12) | (dly_p1 << 20) | (dly_p1 << 28));
 }
@@ -788,11 +788,11 @@ static void dramc_write_dqs_gating_result(u8 chn, u8 rank,
 
 	dramc_rx_dqs_isi_pulse_cg_switch(chn, true);
 
-	clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0,
+	clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0,
 		0x77777777,
 		(best_coarse_tune2t[0] << 0) | (best_coarse_tune2t[1] << 8) |
 		(best_coarse_tune2t_p1[0] << 4) | (best_coarse_tune2t_p1[1] << 12));
-	clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1,
+	clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1,
 		0x77777777,
 		(best_coarse_tune0p5t[0] << 0) | (best_coarse_tune0p5t[1] << 8) |
 		(best_coarse_tune0p5t_p1[0] << 4) | (best_coarse_tune0p5t_p1[1] << 12));
@@ -827,11 +827,11 @@ static void dramc_write_dqs_gating_result(u8 chn, u8 rank,
 		}
 	}
 
-	clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten0,
+	clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_odten0,
 		0x77777777,
 		(best_coarse_rodt[0] << 0) | (best_coarse_rodt[1] << 8) |
 		(best_coarse_rodt_p1[0] << 4) | (best_coarse_rodt_p1[1] << 12));
-	clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_odten1,
+	clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_odten1,
 		0x77777777,
 		(best_coarse_0p5t_rodt[0] << 0) | (best_coarse_0p5t_rodt[1] << 8) |
 		(best_coarse_0p5t_rodt_p1[0] << 4) | (best_coarse_0p5t_rodt_p1[1] << 12));
@@ -1063,7 +1063,7 @@ static void dramc_rx_rd_dqc_init(u8 chn, u8 rank)
 	u16 temp_value = 0;
 
 	for (size_t b = 0; b < 2; b++)
-		clrbits_le32(&ch[chn].phy.shu[0].b[b].dq[7], 0x1 << 7);
+		clrbits32(&ch[chn].phy.shu[0].b[b].dq[7], 0x1 << 7);
 
 	SET32_BITFIELDS(&ch[chn].ao.mrs, MRS_MRSRK, rank);
 	SET32_BITFIELDS(&ch[chn].ao.mpc_option, MPC_OPTION_MPCRKEN, 1);
@@ -1213,17 +1213,17 @@ static void dramc_set_tx_dly_factor(u8 chn, u8 rk,
 
 	if (*dq_small_reg != dly_tune.coarse_tune_small) {
 		if (type == TX_WIN_DQ_DQM || type == TX_WIN_DQ_ONLY) {
-			clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[0],
+			clrsetbits32(&ch[chn].ao.shu[0].rk[rk].selph_dq[0],
 				0x77777777, dly_large | (dly_large_oen << 16));
-			clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[2],
+			clrsetbits32(&ch[chn].ao.shu[0].rk[rk].selph_dq[2],
 				0x77777777, dly_small | (dly_small_oen << 16));
 		}
 
 		if (type == TX_WIN_DQ_DQM) {
 			/* Large coarse_tune setting */
-			clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[1],
+			clrsetbits32(&ch[chn].ao.shu[0].rk[rk].selph_dq[1],
 				0x77777777, dly_large | (dly_large_oen << 16));
-			clrsetbits_le32(&ch[chn].ao.shu[0].rk[rk].selph_dq[3],
+			clrsetbits32(&ch[chn].ao.shu[0].rk[rk].selph_dq[3],
 				0x77777777, dly_small | (dly_small_oen << 16));
 		}
 	}
@@ -1480,13 +1480,13 @@ static void dramc_set_tx_best_dly_factor(u8 chn, u8 rank_start, u8 type,
 	}
 
 	for (size_t rank = rank_start; rank < RANK_MAX; rank++) {
-		clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[0],
+		clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dq[0],
 			0x77777777, dq_large | (dq_large_oen << 16));
-		clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[2],
+		clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dq[2],
 			0x77777777, dq_small | (dq_small_oen << 16));
-		clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[1],
+		clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dq[1],
 			0x77777777, dqm_large | (dqm_large_oen << 16));
-		clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dq[3],
+		clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dq[3],
 			0x77777777, dqm_small | (dqm_small_oen << 16));
 
 		for (size_t byte = 0; byte < 2; byte++)
@@ -1503,15 +1503,15 @@ static void dramc_set_tx_best_dly_factor(u8 chn, u8 rank_start, u8 type,
 		if (type != TX_WIN_DQ_ONLY)
 			continue;
 
-		clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].fine_tune, 0x3f3f3f3f,
+		clrsetbits32(&ch[chn].ao.shu[0].rk[rank].fine_tune, 0x3f3f3f3f,
 			(dqdly_tune[0].fine_tune << 8) | (dqdly_tune[1].fine_tune << 0) |
 			(dqmdly_tune[0].fine_tune << 24) | (dqmdly_tune[1].fine_tune << 16));
 
-		clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal1, 0x7ff | (0x7ff << 16),
+		clrsetbits32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal1, 0x7ff | (0x7ff << 16),
 			(dqdly_tune[0].fine_tune << 0) | (dqdly_tune[1].fine_tune << 16));
-		clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal2, 0x7ff | (0x7ff << 16),
+		clrsetbits32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal2, 0x7ff | (0x7ff << 16),
 			(dqdly_tune[0].fine_tune << 0) | (dqdly_tune[1].fine_tune << 16));
-		clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal5, 0x7ff | (0x7ff << 16),
+		clrsetbits32(&ch[chn].ao.shu[0].rk[rank].dqs2dq_cal5, 0x7ff | (0x7ff << 16),
 			(dqmdly_tune[0].fine_tune << 0) | (dqmdly_tune[1].fine_tune << 16));
 	}
 }
@@ -1525,7 +1525,7 @@ static void dramc_set_rx_best_dly_factor(u8 chn, u8 rank,
 	for (u8 byte = 0; byte < DQS_NUMBER; byte++) {
 		value = (dqsdly_byte[byte] << 24) | (dqsdly_byte[byte] << 16) |
 			(dqmdly_byte[byte] << 8) | (dqmdly_byte[byte] << 0);
-		clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[6], 0x7f7f3f3f, value);
+		clrsetbits32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[6], 0x7f7f3f3f, value);
 	}
 	dram_phy_reset(chn);
 
@@ -1538,7 +1538,7 @@ static void dramc_set_rx_best_dly_factor(u8 chn, u8 rank,
 				(dly[index + 1].best_dqdly << 16) |
 				(dly[index].best_dqdly << 8) | (dly[index].best_dqdly << 0);
 
-			clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[dq_num],
+			clrsetbits32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[dq_num],
 				0x3f3f3f3f, value);
 		}
 	}
@@ -1817,11 +1817,11 @@ static u8 dramc_window_perbit_cal(u8 chn, u8 rank, u8 freq_group,
 	if (type == TX_WIN_DQ_ONLY || type == TX_WIN_DQ_DQM) {
 		for (size_t byte = 0; byte < 2; byte++) {
 			write32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[0], 0);
-			clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[1],
+			clrbits32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[1],
 				0xf);
 		}
-		setbits_le32(&ch[chn].phy.misc_ctrl1, 0x1 << 7);
-		setbits_le32(&ch[chn].ao.dqsoscr, 0x1 << 7);
+		setbits32(&ch[chn].phy.misc_ctrl1, 0x1 << 7);
+		setbits32(&ch[chn].ao.dqsoscr, 0x1 << 7);
 		if (fsp == FSP_1)
 			vref_step = 2;
 	}
@@ -2070,7 +2070,7 @@ static void dramc_rx_dqs_gating_post_process(u8 chn, u8 freq_group)
 					dqs, best_coarse_tune2t_p1[rank][dqs]);
 			}
 
-			clrsetbits_le32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0,
+			clrsetbits32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0,
 				0x77777777,
 				(best_coarse_tune2t[rank][0] << 0) |
 				(best_coarse_tune2t[rank][1] << 8) |
@@ -2085,13 +2085,13 @@ static void dramc_rx_dqs_gating_post_process(u8 chn, u8 freq_group)
 
 	SET32_BITFIELDS(&ch[chn].ao.shu[0].rk[0].dqsctl, SHURK_DQSCTL_DQSINCTL, read_dqsinctl);
 	SET32_BITFIELDS(&ch[chn].ao.shu[0].rk[1].dqsctl, SHURK_DQSCTL_DQSINCTL, read_dqsinctl);
-	clrsetbits_le32(&ch[chn].ao.shu[0].rankctl,
+	clrsetbits32(&ch[chn].ao.shu[0].rankctl,
 		(0xf << 28) | (0xf << 20) | (0xf << 24) | 0xf,
 		(read_dqsinctl << 28) | (rankinctl_root << 20) |
 		(rankinctl_root << 24) | rankinctl_root);
 
 	u8 ROEN = read32(&ch[chn].ao.shu[0].odtctrl) & 0x1;
-	clrsetbits_le32(&ch[chn].ao.shu[0].rodtenstb, (0xffff << 8) | (0x3f << 2) | (0x1),
+	clrsetbits32(&ch[chn].ao.shu[0].rodtenstb, (0xffff << 8) | (0x3f << 2) | (0x1),
 			(0xff << 8) | (0x9 << 2) | ROEN);
 }
 
diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c
index 604592f5cb..7f5ac0a747 100644
--- a/src/soc/mediatek/mt8183/dsi.c
+++ b/src/soc/mediatek/mt8183/dsi.c
@@ -49,19 +49,19 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes)
 		txdiv1 = 0;
 	}
 
-	clrbits_le32(&mipi_tx->pll_con4, BIT(11) | BIT(10));
-	setbits_le32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON);
+	clrbits32(&mipi_tx->pll_con4, BIT(11) | BIT(10));
+	setbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON);
 	udelay(30);
-	clrbits_le32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN);
+	clrbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN);
 
 	pcw = (u64)data_rate * (1 << txdiv0) * (1 << txdiv1);
 	pcw <<= 24;
 	pcw /= CLK26M_HZ / MHz;
 
 	write32(&mipi_tx->pll_con0, pcw);
-	clrsetbits_le32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8);
+	clrsetbits32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8);
 	udelay(30);
-	setbits_le32(&mipi_tx->pll_con1, RG_DSI_PLL_EN);
+	setbits32(&mipi_tx->pll_con1, RG_DSI_PLL_EN);
 
 	/* BG_LPF_EN / BG_CORE_EN */
 	write32(&mipi_tx->lane_con, 0x3fff0180);
@@ -69,13 +69,13 @@ void mtk_dsi_configure_mipi_tx(int data_rate, u32 lanes)
 	write32(&mipi_tx->lane_con, 0x3fff00c0);
 
 	/* Switch OFF each Lane */
-	clrbits_le32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN);
-	clrbits_le32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN);
-	clrbits_le32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN);
-	clrbits_le32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN);
-	clrbits_le32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN);
+	clrbits32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN);
 
-	setbits_le32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN);
+	setbits32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN);
 }
 
 void mtk_dsi_reset(void)
diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c
index 7cd631ca0b..cf104f8485 100644
--- a/src/soc/mediatek/mt8183/emi.c
+++ b/src/soc/mediatek/mt8183/emi.c
@@ -157,7 +157,7 @@ size_t sdram_size(void)
 static void set_rank_info_to_conf(const struct sdram_params *params)
 {
 	bool is_dual_rank = (params->emi_cona_val & (0x1 << 17)) != 0;
-	clrsetbits_le32(&ch[0].ao.rstmask, 0x1 << 12,
+	clrsetbits32(&ch[0].ao.rstmask, 0x1 << 12,
 			(is_dual_rank ? 0 : 1) << 12);
 }
 
@@ -297,8 +297,8 @@ static void emi_init2(const struct sdram_params *params)
 {
 	emi_esl_setting2();
 
-	setbits_le32(&emi_mpu->mpu_ctrl_d[1], 0x1 << 4);
-	setbits_le32(&emi_mpu->mpu_ctrl_d[7], 0x1 << 4);
+	setbits32(&emi_mpu->mpu_ctrl_d[1], 0x1 << 4);
+	setbits32(&emi_mpu->mpu_ctrl_d[7], 0x1 << 4);
 
 	write32(&emi_regs->bwct0, 0x0a000705);
 	write32(&emi_regs->bwct0_3rd, 0x0);
@@ -311,14 +311,14 @@ static void emi_init2(const struct sdram_params *params)
 
 static void dramc_init_pre_settings(void)
 {
-	clrsetbits_le32(&ch[0].phy.ca_cmd[8],
+	clrsetbits32(&ch[0].phy.ca_cmd[8],
 		(0x1 << 21) | (0x1 << 20) | (0x1 << 19) | (0x1 << 18) |
 		(0x1f << 8) | (0x1f << 0),
 		(0x1 << 19) | (0xa << 8) | (0xa << 0));
 
-	setbits_le32(&ch[0].phy.misc_ctrl1, 0x1 << 12);
-	clrbits_le32(&ch[0].phy.misc_ctrl1, 0x1 << 13);
-	setbits_le32(&ch[0].phy.misc_ctrl1, 0x1 << 31);
+	setbits32(&ch[0].phy.misc_ctrl1, 0x1 << 12);
+	clrbits32(&ch[0].phy.misc_ctrl1, 0x1 << 13);
+	setbits32(&ch[0].phy.misc_ctrl1, 0x1 << 31);
 }
 
 static void dramc_ac_timing_optimize(u8 freq_group)
@@ -331,20 +331,20 @@ static void dramc_ac_timing_optimize(u8 freq_group)
 	};
 
 	for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
-		clrsetbits_le32(&ch[chn].ao.shu[0].actim[3],
+		clrsetbits32(&ch[chn].ao.shu[0].actim[3],
 			0xff << 16, rf_cab_opt[freq_group].rfc << 16);
-		clrbits_le32(&ch[chn].ao.shu[0].ac_time_05t,
+		clrbits32(&ch[chn].ao.shu[0].ac_time_05t,
 			rf_cab_opt[freq_group].rfc_05t << 2);
-		clrsetbits_le32(&ch[chn].ao.shu[0].actim[4],
+		clrsetbits32(&ch[chn].ao.shu[0].actim[4],
 			0x3ff << 0, rf_cab_opt[freq_group].tx_ref_cnt << 0);
 	}
 }
 
 static void spm_pinmux_setting(void)
 {
-	clrsetbits_le32(&mtk_spm->poweron_config_set,
+	clrsetbits32(&mtk_spm->poweron_config_set,
 		(0xffff << 16) | (0x1 << 0), (0xb16 << 16) | (0x1 << 0));
-	clrbits_le32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16));
+	clrbits32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16));
 	write32(&mtk_spm->dramc_dpy_clk_sw_con_sel, 0xffffffff);
 	write32(&mtk_spm->dramc_dpy_clk_sw_con_sel2, 0xffffffff);
 }
@@ -377,11 +377,11 @@ static void init_dram(const struct sdram_params *params, u8 freq_group,
 
 void enable_emi_dcm(void)
 {
-	clrbits_le32(&emi_regs->conm, 0xff << 24);
-	clrbits_le32(&emi_regs->conn, 0xff << 24);
+	clrbits32(&emi_regs->conm, 0xff << 24);
+	clrbits32(&emi_regs->conn, 0xff << 24);
 
 	for (size_t chn = 0; chn < CHANNEL_MAX; chn++)
-		clrbits_le32(&ch[chn].emi.chn_conb, 0xff << 24);
+		clrbits32(&ch[chn].emi.chn_conb, 0xff << 24);
 }
 
 struct shuffle_reg_addr {
@@ -456,18 +456,18 @@ static void dramc_save_result_to_shuffle(u32 src_shuffle, u32 dst_shuffle)
 		value = read32(src_addr) & 0x7f;
 
 		if (dst_shuffle == DRAM_DFS_SHUFFLE_2)
-			clrsetbits_le32(dst_addr, 0x7f << 0x8, value << 0x8);
+			clrsetbits32(dst_addr, 0x7f << 0x8, value << 0x8);
 		else if (dst_shuffle == DRAM_DFS_SHUFFLE_3)
-			clrsetbits_le32(dst_addr, 0x7f << 0x16, value << 0x16);
+			clrsetbits32(dst_addr, 0x7f << 0x16, value << 0x16);
 
 		/* DRAMC-exception-2 */
 		src_addr = (u8 *)&ch[chn].ao.dvfsdll;
 		value = (read32(src_addr) >> 1) & 0x1;
 
 		if (dst_shuffle == DRAM_DFS_SHUFFLE_2)
-			clrsetbits_le32(src_addr, 0x1 << 2, value << 2);
+			clrsetbits32(src_addr, 0x1 << 2, value << 2);
 		else if (dst_shuffle == DRAM_DFS_SHUFFLE_3)
-			clrsetbits_le32(src_addr, 0x1 << 3, value << 3);
+			clrsetbits32(src_addr, 0x1 << 3, value << 3);
 
 		/* PHY */
 		for (index = 0; index < ARRAY_SIZE(phy_regs); index++) {
diff --git a/src/soc/mediatek/mt8183/gpio.c b/src/soc/mediatek/mt8183/gpio.c
index 3eccfbd50d..0664678dd9 100644
--- a/src/soc/mediatek/mt8183/gpio.c
+++ b/src/soc/mediatek/mt8183/gpio.c
@@ -34,15 +34,15 @@ static void gpio_set_pull_pupd(gpio_t gpio, enum pull_enable enable,
 
 	if (enable == GPIO_PULL_ENABLE) {
 		if (select == GPIO_PULL_DOWN)
-			setbits_le32(reg, 1 << (bit + 2));
+			setbits32(reg, 1 << (bit + 2));
 		else
-			clrbits_le32(reg, 1 << (bit + 2));
+			clrbits32(reg, 1 << (bit + 2));
 	}
 
 	if (enable == GPIO_PULL_ENABLE)
-		clrsetbits_le32(reg, 3 << bit, 1 << bit);
+		clrsetbits32(reg, 3 << bit, 1 << bit);
 	else
-		clrbits_le32(reg, 3 << bit);
+		clrbits32(reg, 3 << bit);
 }
 
 static void gpio_set_pull_en_sel(gpio_t gpio, enum pull_enable enable,
@@ -53,15 +53,15 @@ static void gpio_set_pull_en_sel(gpio_t gpio, enum pull_enable enable,
 
 	if (enable == GPIO_PULL_ENABLE) {
 		if (select == GPIO_PULL_DOWN)
-			clrbits_le32(reg + SEL_OFFSET, 1 << bit);
+			clrbits32(reg + SEL_OFFSET, 1 << bit);
 		else
-			setbits_le32(reg + SEL_OFFSET, 1 << bit);
+			setbits32(reg + SEL_OFFSET, 1 << bit);
 	}
 
 	if (enable == GPIO_PULL_ENABLE)
-		setbits_le32(reg + EN_OFFSET, 1 << bit);
+		setbits32(reg + EN_OFFSET, 1 << bit);
 	else
-		clrbits_le32(reg + EN_OFFSET, 1 << bit);
+		clrbits32(reg + EN_OFFSET, 1 << bit);
 }
 
 void gpio_set_pull(gpio_t gpio, enum pull_enable enable,
@@ -112,23 +112,23 @@ enum {
 
 void gpio_set_i2c_eh_rsel(void)
 {
-	clrsetbits_le32((void *)IOCFG_RB_BASE + EH_RSEL_OFFSET,
+	clrsetbits32((void *)IOCFG_RB_BASE + EH_RSEL_OFFSET,
 		I2C_EH_RSL_MASK(SCL0) | I2C_EH_RSL_MASK(SDA0) |
 		I2C_EH_RSL_MASK(SCL1) | I2C_EH_RSL_MASK(SDA1),
 		I2C_EH_RSL_VAL(SCL0) | I2C_EH_RSL_VAL(SDA0) |
 		I2C_EH_RSL_VAL(SCL1) | I2C_EH_RSL_VAL(SDA1));
 
-	clrsetbits_le32((void *)IOCFG_RM_BASE + EH_RSEL_OFFSET,
+	clrsetbits32((void *)IOCFG_RM_BASE + EH_RSEL_OFFSET,
 		I2C_EH_RSL_MASK(SCL2) | I2C_EH_RSL_MASK(SDA2) |
 		I2C_EH_RSL_MASK(SCL4) | I2C_EH_RSL_MASK(SDA4),
 		I2C_EH_RSL_VAL(SCL2) | I2C_EH_RSL_VAL(SDA2) |
 		I2C_EH_RSL_VAL(SCL4) | I2C_EH_RSL_VAL(SDA4));
 
-	clrsetbits_le32((void *)IOCFG_BL_BASE + EH_RSEL_OFFSET,
+	clrsetbits32((void *)IOCFG_BL_BASE + EH_RSEL_OFFSET,
 		I2C_EH_RSL_MASK(SCL3) | I2C_EH_RSL_MASK(SDA3),
 		I2C_EH_RSL_VAL(SCL3) | I2C_EH_RSL_VAL(SDA3));
 
-	clrsetbits_le32((void *)IOCFG_LB_BASE + EH_RSEL_OFFSET,
+	clrsetbits32((void *)IOCFG_LB_BASE + EH_RSEL_OFFSET,
 		I2C_EH_RSL_MASK(SCL5) | I2C_EH_RSL_MASK(SDA5),
 		I2C_EH_RSL_VAL(SCL5) | I2C_EH_RSL_VAL(SDA5));
 }
@@ -153,17 +153,17 @@ void gpio_set_spi_driving(unsigned int bus, enum spi_pad_mask pad_select,
 			reg = (void *)(IOCFG_LM_BASE + GPIO_DRV0_OFFSET);
 			offset = 0;
 		} else if (pad_select == SPI_PAD1_MASK) {
-			clrsetbits_le32((void *)IOCFG_RM_BASE +
+			clrsetbits32((void *)IOCFG_RM_BASE +
 					GPIO_DRV0_OFFSET, 0xf | 0xf << 20,
 					reg_val | reg_val << 20);
-			clrsetbits_le32((void *)IOCFG_RM_BASE +
+			clrsetbits32((void *)IOCFG_RM_BASE +
 					GPIO_DRV1_OFFSET, 0xf << 16,
 					reg_val << 16);
 			return;
 		}
 		break;
 	case 2:
-		clrsetbits_le32((void *)IOCFG_RM_BASE + GPIO_DRV0_OFFSET,
+		clrsetbits32((void *)IOCFG_RM_BASE + GPIO_DRV0_OFFSET,
 				0xf << 8 | 0xf << 12,
 				reg_val << 8 | reg_val << 12);
 		return;
@@ -181,5 +181,5 @@ void gpio_set_spi_driving(unsigned int bus, enum spi_pad_mask pad_select,
 		break;
 	}
 
-	clrsetbits_le32(reg, 0xf << offset, reg_val << offset);
+	clrsetbits32(reg, 0xf << offset, reg_val << offset);
 }
diff --git a/src/soc/mediatek/mt8183/md_ctrl.c b/src/soc/mediatek/mt8183/md_ctrl.c
index aa97756db2..a1405dd0e7 100644
--- a/src/soc/mediatek/mt8183/md_ctrl.c
+++ b/src/soc/mediatek/mt8183/md_ctrl.c
@@ -24,10 +24,10 @@
 static void internal_md_power_down(void)
 {
 	/* Gating MD clock */
-	setbits_le32(&mtk_topckgen->clk_mode,
+	setbits32(&mtk_topckgen->clk_mode,
 		TOPCKGEN_CLK_MODE_MD_32K | TOPCKGEN_CLK_MODE_MD_26M);
 	/* Release SRCCLKENA */
-	clrbits_le32(&mt8183_infracfg->infra_misc2,
+	clrbits32(&mt8183_infracfg->infra_misc2,
 		INFRA_MISC2_SRCCLKENA_RELEASE);
 }
 
diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c
index 5368077318..ff61303337 100644
--- a/src/soc/mediatek/mt8183/pll.c
+++ b/src/soc/mediatek/mt8183/pll.c
@@ -282,7 +282,7 @@ static const struct rate rates[] = {
 
 void pll_set_pcw_change(const struct pll *pll)
 {
-	setbits_le32(pll->div_reg, PLL_PCW_CHG);
+	setbits32(pll->div_reg, PLL_PCW_CHG);
 }
 
 void mt_pll_init(void)
@@ -290,20 +290,20 @@ void mt_pll_init(void)
 	int i;
 
 	/* enable univpll & mainpll div */
-	setbits_le32(&mtk_apmixed->ap_pll_con2, 0x1FFE << 16);
+	setbits32(&mtk_apmixed->ap_pll_con2, 0x1FFE << 16);
 
 	/* enable clock square1 low-pass filter */
-	setbits_le32(&mtk_apmixed->ap_pll_con0, 0x2);
+	setbits32(&mtk_apmixed->ap_pll_con0, 0x2);
 
 	/* xPLL PWR ON */
 	for (i = 0; i < APMIXED_PLL_MAX; i++)
-		setbits_le32(plls[i].pwr_reg, PLL_PWR_ON);
+		setbits32(plls[i].pwr_reg, PLL_PWR_ON);
 
 	udelay(PLL_PWR_ON_DELAY);
 
 	/* xPLL ISO Disable */
 	for (i = 0; i < APMIXED_PLL_MAX; i++)
-		clrbits_le32(plls[i].pwr_reg, PLL_ISO);
+		clrbits32(plls[i].pwr_reg, PLL_ISO);
 
 	udelay(PLL_ISO_DELAY);
 
@@ -319,7 +319,7 @@ void mt_pll_init(void)
 
 	/* xPLL Frequency Enable */
 	for (i = 0; i < APMIXED_PLL_MAX; i++)
-		setbits_le32(plls[i].reg, PLL_EN);
+		setbits32(plls[i].reg, PLL_EN);
 
 	/* wait for PLL stable */
 	udelay(PLL_EN_DELAY);
@@ -327,32 +327,32 @@ void mt_pll_init(void)
 	/* xPLL DIV RSTB */
 	for (i = 0; i < APMIXED_PLL_MAX; i++) {
 		if (plls[i].rstb_shift != NO_RSTB_SHIFT)
-			setbits_le32(plls[i].reg, 1 << plls[i].rstb_shift);
+			setbits32(plls[i].reg, 1 << plls[i].rstb_shift);
 	}
 
 	/* MCUCFG CLKMUX */
-	clrsetbits_le32(&mt8183_mcucfg->mp0_pll_divider_cfg, DIV_MASK, DIV_1);
-	clrsetbits_le32(&mt8183_mcucfg->mp2_pll_divider_cfg, DIV_MASK, DIV_1);
-	clrsetbits_le32(&mt8183_mcucfg->bus_pll_divider_cfg, DIV_MASK, DIV_2);
+	clrsetbits32(&mt8183_mcucfg->mp0_pll_divider_cfg, DIV_MASK, DIV_1);
+	clrsetbits32(&mt8183_mcucfg->mp2_pll_divider_cfg, DIV_MASK, DIV_1);
+	clrsetbits32(&mt8183_mcucfg->bus_pll_divider_cfg, DIV_MASK, DIV_2);
 
-	clrsetbits_le32(&mt8183_mcucfg->mp0_pll_divider_cfg, MUX_MASK,
+	clrsetbits32(&mt8183_mcucfg->mp0_pll_divider_cfg, MUX_MASK,
 		MUX_SRC_ARMPLL);
-	clrsetbits_le32(&mt8183_mcucfg->mp2_pll_divider_cfg, MUX_MASK,
+	clrsetbits32(&mt8183_mcucfg->mp2_pll_divider_cfg, MUX_MASK,
 		MUX_SRC_ARMPLL);
-	clrsetbits_le32(&mt8183_mcucfg->bus_pll_divider_cfg, MUX_MASK,
+	clrsetbits32(&mt8183_mcucfg->bus_pll_divider_cfg, MUX_MASK,
 		MUX_SRC_ARMPLL);
 
 	/* enable infrasys DCM */
-	setbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl, 0x3 << 21);
-	clrsetbits_le32(&mt8183_infracfg->infra_bus_dcm_ctrl,
+	setbits32(&mt8183_infracfg->infra_bus_dcm_ctrl, 0x3 << 21);
+	clrsetbits32(&mt8183_infracfg->infra_bus_dcm_ctrl,
 		DCM_INFRA_BUS_MASK, DCM_INFRA_BUS_ON);
-	setbits_le32(&mt8183_infracfg->mem_dcm_ctrl, DCM_INFRA_MEM_ON);
-	clrbits_le32(&mt8183_infracfg->p2p_rx_clk_on, DCM_INFRA_P2PRX_MASK);
-	clrsetbits_le32(&mt8183_infracfg->peri_bus_dcm_ctrl,
+	setbits32(&mt8183_infracfg->mem_dcm_ctrl, DCM_INFRA_MEM_ON);
+	clrbits32(&mt8183_infracfg->p2p_rx_clk_on, DCM_INFRA_P2PRX_MASK);
+	clrsetbits32(&mt8183_infracfg->peri_bus_dcm_ctrl,
 		DCM_INFRA_PERI_MASK, DCM_INFRA_PERI_ON);
 
 	/* enable [11] for change i2c module source clock to TOPCKGEN */
-	setbits_le32(&mt8183_infracfg->module_clk_sel, 0x1 << 11);
+	setbits32(&mt8183_infracfg->module_clk_sel, 0x1 << 11);
 
 	/*
 	 * TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
@@ -361,19 +361,19 @@ void mt_pll_init(void)
 		mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
 
 	/* enable [14] dramc_pll104m_ck */
-	setbits_le32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);
+	setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);
 
 	/* enable audio clock */
-	setbits_le32(&mtk_topckgen->clk_cfg_5_clr, 1 << 7);
+	setbits32(&mtk_topckgen->clk_cfg_5_clr, 1 << 7);
 
 	/* enable intbus clock */
-	setbits_le32(&mtk_topckgen->clk_cfg_5_clr, 1 << 15);
+	setbits32(&mtk_topckgen->clk_cfg_5_clr, 1 << 15);
 
 	/* enable infra clock */
-	setbits_le32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 25);
+	setbits32(&mt8183_infracfg->module_sw_cg_1_clr, 1 << 25);
 
 	/* enable mtkaif 26m clock */
-	setbits_le32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4);
+	setbits32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4);
 }
 
 void mt_pll_raise_ca53_freq(u32 freq)
diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c
index 7672db7993..c77d7ef7d3 100644
--- a/src/soc/mediatek/mt8183/spi.c
+++ b/src/soc/mediatek/mt8183/spi.c
@@ -127,10 +127,10 @@ void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks,
 		((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) |
 		((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT));
 
-	clrsetbits_le32(&regs->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK |
-			SPI_CFG1_CS_IDLE_MASK,
-			(tick_dly << SPI_CFG1_TICK_DLY_SHIFT) |
-			((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT));
+	clrsetbits32(&regs->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK |
+		     SPI_CFG1_CS_IDLE_MASK,
+		     (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) |
+		     ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT));
 }
 
 const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c
index 9a08782953..024fe1c9fc 100644
--- a/src/soc/mediatek/mt8183/spm.c
+++ b/src/soc/mediatek/mt8183/spm.c
@@ -77,16 +77,16 @@ static int spm_register_init(void)
 		MD_DDR_EN_1_DBC_LEN |
 		CONN_DDR_EN_DBC_LEN);
 
-	clrsetbits_le32(&mtk_spm->spare_ack_mask,
-			SPARE_ACK_MASK_B_BIT1,
-			SPARE_ACK_MASK_B_BIT0);
+	clrsetbits32(&mtk_spm->spare_ack_mask,
+		     SPARE_ACK_MASK_B_BIT1,
+		     SPARE_ACK_MASK_B_BIT0);
 
 	write32(&mtk_spm->sysrom_con, IFR_SRAMROM_ROM_PDN);
 	write32(&mtk_spm->spm_pc_trace_con,
 		SPM_PC_TRACE_OFFSET |
 		SPM_PC_TRACE_HW_EN_LSB);
 
-	setbits_le32(&mtk_spm->spare_src_req_mask, SPARE1_DDREN_MASK_B_LSB);
+	setbits32(&mtk_spm->spare_src_req_mask, SPARE1_DDREN_MASK_B_LSB);
 
 	return 0;
 }
@@ -131,9 +131,9 @@ static int spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc)
 
 	write32(&mtk_spm->pcm_pwr_io_en, 0);
 
-	clrsetbits_le32(&mtk_spm->pcm_con1,
-			PCM_TIMER_EN_LSB,
-			SPM_REGWR_CFG_KEY);
+	clrsetbits32(&mtk_spm->pcm_con1,
+		     PCM_TIMER_EN_LSB,
+		     SPM_REGWR_CFG_KEY);
 
 	write32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB |
 		PCM_SW_RESET_LSB);
diff --git a/src/soc/mediatek/mt8183/sspm.c b/src/soc/mediatek/mt8183/sspm.c
index 559034eacb..857d3dc56d 100644
--- a/src/soc/mediatek/mt8183/sspm.c
+++ b/src/soc/mediatek/mt8183/sspm.c
@@ -16,7 +16,7 @@
 #include <arch/barrier.h>
 #include <cbfs.h>
 #include <console/console.h>
-#include <arch/mmio.h>
+#include <device/mmio.h>
 #include <soc/sspm.h>
 #include <string.h>