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| author | Yidi Lin <yidi.lin@mediatek.com> | 2020-11-06 17:52:56 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-11-20 08:40:58 +0000 |
| commit | 2832d11dd1aa59a195c67296a2a39ae4689b74eb (patch) | |
| tree | 110d90fb62790cc16f05d26367459490589d9114 /src/soc/mediatek/mt8192/Makefile.inc | |
| parent | f06dd678e6bc916d29335b945f54d732b31e1ee2 (diff) | |
| download | coreboot-2832d11dd1aa59a195c67296a2a39ae4689b74eb.tar.xz | |
mediatek/mt8192: memlayout: Add DRAM DMA region
SPM DMA hardware requires a non-cacheable buffer to load SPM
firmware.
TEST=verified with SPM WIP patch.
SPM PC stays at 0x3f4 after SPM firmware is loaded.
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: If6e803da23126419a96ffc0337d35edd0e181871
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8192/Makefile.inc')
| -rw-r--r-- | src/soc/mediatek/mt8192/Makefile.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 07a13af5f3..421968d85a 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -26,7 +26,7 @@ romstage-y += ../common/cbmem.c romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c -romstage-y += ../common/mmu_operations.c +romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += memory.c dramc_param.c ../common/memory_test.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c |