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| author | Weiyi Lu <weiyi.lu@mediatek.com> | 2021-02-03 16:20:57 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-04-28 02:42:03 +0000 |
| commit | 450fd0b536fd1bd956ee575716cfc6b8b8b46bab (patch) | |
| tree | e1774cf4dbbef1fd34764cc31fafcb5d10e44d11 /src/soc/mediatek/mt8195/Makefile.inc | |
| parent | 2368a310be4bf60ea9c83fc89e89be9d6a040775 (diff) | |
| download | coreboot-450fd0b536fd1bd956ee575716cfc6b8b8b46bab.tar.xz | |
soc/mediatek/mt8195: Add PLL and clock init support
Add PLL and clock init code.
Add frequency meter and API for raising little CPU/CCI frequency.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: I8ded0236d10826687f080bd5a213feb55d4bae03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52667
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8195/Makefile.inc')
| -rw-r--r-- | src/soc/mediatek/mt8195/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 0da0cef70b..b3e12e95f2 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -3,6 +3,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8195),y) bootblock-y += bootblock.c bootblock-y += ../common/gpio.c gpio.c bootblock-y += ../common/mmu_operations.c +bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += spi.c bootblock-y += ../common/timer.c timer.c bootblock-y += ../common/uart.c @@ -17,6 +18,7 @@ verstage-y += ../common/wdt.c romstage-y += ../common/cbmem.c romstage-y += emi.c romstage-y += ../common/gpio.c gpio.c +romstage-y += ../common/pll.c pll.c romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-y += ../common/timer.c timer.c romstage-y += ../common/uart.c |