diff options
| author | Yidi Lin <yidi.lin@mediatek.com> | 2016-01-18 11:06:19 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-03-12 09:14:18 +0100 |
| commit | 9a64ec4dd239f2b757dff9effe3b10510034e62c (patch) | |
| tree | 5b5bfeb1fabb78d73c57e0410a4663dd19ae1c31 /src/soc/mediatek | |
| parent | fd99eca8001c9178b3b2b15ca7d76437305c31aa (diff) | |
| download | coreboot-9a64ec4dd239f2b757dff9effe3b10510034e62c.tar.xz | |
mediatek/mt8173: mmu: update mmu range before DRAM is initialized.
The DRAM size can not be determined before DRAM is initialized. Since
mt8173 only support 2GB and 4GB DRAM models. We map 0x0 to the end of
2GB DRAM address before DRAM is initialized.
BRANCH=none
BUG=none
TEST=boot to kernel
Change-Id: I27a00106b0aa91c3dacfcd2bcd9208f08b108dc5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9720e67c86f0d37a08f7c32e900996c75d60288a
Original-Change-Id: I87d9c6ac11486decde102b7821f550c2f1a51f1c
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327960
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/331175
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13987
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/mediatek')
| -rw-r--r-- | src/soc/mediatek/mt8173/mmu_operations.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/mediatek/mt8173/mmu_operations.c b/src/soc/mediatek/mt8173/mmu_operations.c index a70fe2ccaa..744248acdf 100644 --- a/src/soc/mediatek/mt8173/mmu_operations.c +++ b/src/soc/mediatek/mt8173/mmu_operations.c @@ -30,8 +30,8 @@ void mt8173_mmu_init(void) { mmu_init(); - /* Set 0x0 to end of dram as device memory */ - mmu_config_range((void *)0, (uintptr_t)_dram + dram_size, DEV_MEM); + /* Set 0x0 to the end of 2GB dram address as device memory */ + mmu_config_range((void *)0, (uintptr_t)_dram + 2U * GiB, DEV_MEM); /* SRAM is cached */ mmu_config_range(_sram_l2c, _sram_l2c_size + _sram_size, CACHED_MEM); @@ -47,7 +47,7 @@ void mt8173_mmu_init(void) void mt8173_mmu_after_dram(void) { - /* Remap DRAM as cached now that it's up and running */ + /* Map DRAM as cached now that it's up and running */ mmu_config_range(_dram, dram_size, CACHED_MEM); /* Unmap L2C SRAM so it can be reclaimed by L2 cache */ |