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authorJulius Werner <jwerner@chromium.org>2019-10-02 17:28:56 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-12-02 22:12:10 +0000
commitbaf27dbaeb1f6791ebfc416f2175507686bd88ac (patch)
tree55c9d8224cde44d732b183624abf76b7446e418e /src/soc/mediatek
parent4a1cbdd51aafa671ecb6c93a475ca9bf6f9ca914 (diff)
downloadcoreboot-baf27dbaeb1f6791ebfc416f2175507686bd88ac.tar.xz
cbfs: Enable CBFS mcache on most chipsets
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with. Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/mediatek')
-rw-r--r--src/soc/mediatek/mt8173/memlayout.ld3
-rw-r--r--src/soc/mediatek/mt8183/memlayout.ld3
-rw-r--r--src/soc/mediatek/mt8192/include/soc/memlayout.ld7
3 files changed, 8 insertions, 5 deletions
diff --git a/src/soc/mediatek/mt8173/memlayout.ld b/src/soc/mediatek/mt8173/memlayout.ld
index 4aece51cef..d9a6d8312d 100644
--- a/src/soc/mediatek/mt8173/memlayout.ld
+++ b/src/soc/mediatek/mt8173/memlayout.ld
@@ -30,7 +30,8 @@ SECTIONS
FMAP_CACHE(0x00103800, 2K)
PRERAM_CBMEM_CONSOLE(0x00104000, 12K)
WATCHDOG_TOMBSTONE(0x00107000, 4)
- PRERAM_CBFS_CACHE(0x00107004, 16K - 4)
+ PRERAM_CBFS_CACHE(0x00107004, 8K - 4)
+ CBFS_MCACHE(0x00109000, 8K)
TIMESTAMP(0x0010B000, 4K)
ROMSTAGE(0x0010C000, 92K)
STACK(0x00124000, 16K)
diff --git a/src/soc/mediatek/mt8183/memlayout.ld b/src/soc/mediatek/mt8183/memlayout.ld
index a26637766b..db566665c2 100644
--- a/src/soc/mediatek/mt8183/memlayout.ld
+++ b/src/soc/mediatek/mt8183/memlayout.ld
@@ -30,7 +30,8 @@ SECTIONS
SRAM_L2C_START(0x00200000)
OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00201000, 188K)
- BOOTBLOCK(0x00230000, 64K)
+ BOOTBLOCK(0x00230000, 56K)
+ CBFS_MCACHE(0x0023e000, 8K)
DRAM_INIT_CODE(0x00240000, 208K)
PRERAM_CBFS_CACHE(0x00274000, 48K)
SRAM_L2C_END(0x00280000)
diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld
index c016d5faa7..2a21dd6ba8 100644
--- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld
@@ -26,9 +26,10 @@ SECTIONS
TPM_TCPA_LOG(0x00103000, 2K)
FMAP_CACHE(0x00103800, 2K)
WATCHDOG_TOMBSTONE(0x00104000, 4)
- PRERAM_CBMEM_CONSOLE(0x00104004, 19K - 4)
- TIMESTAMP(0x00108c00, 1K)
- STACK(0x00109000, 16K)
+ PRERAM_CBMEM_CONSOLE(0x00104004, 15K - 4)
+ CBFS_MCACHE(0x00107c00, 8K)
+ TIMESTAMP(0x00109c00, 1K)
+ STACK(0x0010a000, 12K)
TTB(0x0010d000, 28K)
DMA_COHERENT(0x00114000, 4K)
/*