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authorWeiyi Lu <weiyi.lu@mediatek.com>2019-08-05 17:45:24 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-09-04 10:56:09 +0000
commite78d140b1193f09d5510316d610283ee2f2c8b15 (patch)
treed912ee5d622a7cb1e6b04316eeca54f865ea8bde /src/soc/mediatek
parentbcbf2deb42362232eb5e1414c5d99026f045e2e4 (diff)
downloadcoreboot-e78d140b1193f09d5510316d610283ee2f2c8b15.tar.xz
mediatek/mt8183: postpone dcxo low power mode setting
Consider the association between modem[1] and DCXO, this patch is a fix for eb5e47d("mediatek/mt8183: update dcxo output buffer setting") [2] We should not disable XO_CEL and block the bblpm request when modem is still ON. For power-saving, we still could disable unused XO_CEL and mask request to disable unused power mode when modem is no longer be used. [1] https://review.coreboot.org/c/coreboot/+/32666 [2] https://review.coreboot.org/c/coreboot/+/32323 BRANCH=none TEST=Boots correctly on Krane. Change-Id: I047ebed615e874977ca211aafd52b5551c71b764 Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/mediatek')
-rw-r--r--src/soc/mediatek/mt8183/include/soc/rtc.h2
-rw-r--r--src/soc/mediatek/mt8183/rtc.c13
-rw-r--r--src/soc/mediatek/mt8183/soc.c2
3 files changed, 14 insertions, 3 deletions
diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h
index 5a61208eee..bf120e9387 100644
--- a/src/soc/mediatek/mt8183/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8183/include/soc/rtc.h
@@ -147,6 +147,7 @@ enum {
/* PMIC DCXO Register Definition */
enum {
PMIC_RG_DCXO_CW00 = 0x0788,
+ PMIC_RG_DCXO_CW00_CLR = 0x078C,
PMIC_RG_DCXO_CW02 = 0x0790,
PMIC_RG_DCXO_CW07 = 0x079A,
PMIC_RG_DCXO_CW09 = 0x079E,
@@ -218,5 +219,6 @@ void rtc_bbpu_power_on(void);
void rtc_osc_init(void);
int rtc_init(u8 recover);
void rtc_boot(void);
+void mt6358_dcxo_disable_unused(void);
#endif /* SOC_MEDIATEK_MT8183_RTC_H */
diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c
index f8d81f8c39..19b717cc82 100644
--- a/src/soc/mediatek/mt8183/rtc.c
+++ b/src/soc/mediatek/mt8183/rtc.c
@@ -411,10 +411,9 @@ static void dcxo_init(void)
rtc_write(PMIC_RG_DCXO_CW16, 0x9855);
/* 26M enable control */
- /* Enable clock buffer XO_SOC */
- rtc_write(PMIC_RG_DCXO_CW00, 0x4005);
+ /* Enable clock buffer XO_SOC, XO_CEL */
+ rtc_write(PMIC_RG_DCXO_CW00, 0x4805);
rtc_write(PMIC_RG_DCXO_CW11, 0x8000);
- rtc_write(PMIC_RG_DCXO_CW23, 0x0053);
/* Load thermal coefficient */
rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7);
@@ -432,6 +431,14 @@ static void dcxo_init(void)
mdelay(5);
}
+void mt6358_dcxo_disable_unused(void)
+{
+ /* Disable clock buffer XO_CEL */
+ rtc_write(PMIC_RG_DCXO_CW00_CLR, 0x0800);
+ /* Mask bblpm */
+ rtc_write(PMIC_RG_DCXO_CW23, 0x0053);
+}
+
/* the rtc boot flow entry */
void rtc_boot(void)
{
diff --git a/src/soc/mediatek/mt8183/soc.c b/src/soc/mediatek/mt8183/soc.c
index c9c2147cc8..21b2f811d6 100644
--- a/src/soc/mediatek/mt8183/soc.c
+++ b/src/soc/mediatek/mt8183/soc.c
@@ -17,6 +17,7 @@
#include <soc/emi.h>
#include <soc/md_ctrl.h>
#include <soc/mmu_operations.h>
+#include <soc/rtc.h>
#include <soc/sspm.h>
#include <symbols.h>
@@ -29,6 +30,7 @@ static void soc_init(struct device *dev)
{
mtk_mmu_disable_l2c_sram();
mtk_md_early_init();
+ mt6358_dcxo_disable_unused();
sspm_init();
}